A 4GHz CT ΔΣ ADC with 70dB DR and –74dBFS THD in 125MHz BW

📋 论文概要

该论文提出了一种高速连续时间ΔΣ ADC拓扑，通过吸收量化器输入电容引起的极点并利用本地反馈环路补偿量化器的过量延迟，实现了在GHz采样率下的高分辨率多比特ΔΣ ADC。该ADC的带宽比现有技术宽6倍，并在功耗效率上达到与先进流水线BiCMOS ADC相当的水平。

💡 主要创新点

• 提出了一种吸收量化器输入电容引起的极点的拓扑结构，消除了其对高速性能的限制。
• 引入本地反馈环路补偿量化器的过量延迟，使多比特ΔΣ ADC能在GHz采样率下稳定工作。

🏷 关键词

📄 原文摘要

2 NXP Semiconductors, Eindhoven, The Netherlands Delft University of Technology, Delft, The Netherlands In this paper, a high-speed continuous-time (CT) ΔΣ ADC topology is proposed that absorbs the pole normally caused by the quantizer’s input capacitance, while a local feedback loop compensates for the quantizer’s excess delay. These measures allow a high-resolution multi-bit ΔΣ ADC to operate at GHz sampling rates. The bandwidth of this CMOS ΔΣ ADC is 6× wider than the state-of-the-art [1, 2]. Compared to a state-of-the-art pipeline BiCMOS ADC [3], it achieves similar power efficiency and bandwidth, but it only occupies 0.9mm2 in 45nm CMOS, which is essential for low-cost integration. The 4b 3rd-order CT ΔΣ ADC is sampled at 4GHz and achieves 70dB DR and –74dBFS THD in a 125MHz BW while consuming 256mW. This prototype enables the use of ΔΣ ADCs in applications such as GSM base-stations and HD video systems.

👥 作者与机构

Muhammed Bolatkale1, Lucien J. Breems1, Robert Rutten1, Kofi A.A. Makinwa2