A 12b 1GS/s SiGe BiCMOS Two-Way TimeInterleaved Pipeline ADC drives the top-plate sampling switch (M1) and achieves high SFDR. A 20Ω resistor between M1 and the 600fF sampling capacitor improves the linearity of M1.

📋 论文概要

本文提出了一种12位1GS/s的双路时间交织流水线ADC，采用SiGe BiCMOS工艺。通过模拟校准技术解决分支间失配问题，包括利用10位DAC调整时钟缓冲器电源来校正定时偏移，以及改变自举电路电源来调整带宽。

💡 主要创新点

• 采用模拟校准技术分别调整定时偏移和带宽，通过改变电源电压控制时钟缓冲器传播延迟和自举电路导通电阻。
• 共享其他电路，仅输出射极跟随器(Q3)存在增益失配且无需校准，简化了设计。

🏷 关键词

📄 原文摘要

Marco Corsi1, David Smith1, Noam Tal2 Analog calibration techniques address the mismatches between branches. Timing skew is adjusted using a 10b DAC to supply the clock buffer power supply which changes its propagation delay. BW is adjusted similarly by changing the power supply to the bootstrap circuit to vary the on-resistance of M1. Since all other circuits are shared, the only gain mismatch between branches is the output EF (Q3) which did not need calibration. 10.2 1 2 Texas Instruments, Dallas, TX Texas Instruments, Raanana, Israel Pipelined ADCs designed in analog BiCMOS technologies can offer good linearity and high SNR performance for input signals with reasonable voltage swings. Such ADCs, however, face two critical design challenges: the process limits the sampling rate, and the pipeline architecture limits power efficiency. This paper introduces a two-way time-interleaved (TI) switched-current 1Gs/s 12b pipelined

👥 作者与机构

Robert Payne1, Charles Sestok1, William Bright1, Manar El-Chammas1,