Analog-DFE-Based 16Gb/s SerDes in 40nm CMOS That Operates Across 34dB Loss Channels at Nyquist with a Baud Rate CDR and 1.2Vpp Voltage-Mode Driver

📋 论文概要

该论文提出了一种基于模拟决策反馈均衡器（DFE）的16Gb/s串行解串器（SerDes），采用40nm CMOS工艺，能够在Nyquist频率下通过34dB损耗的背板通道工作，并集成了波特率时钟数据恢复（CDR）电路。解决了高速背板通信中高损耗通道的均衡和时钟恢复问题。

💡 主要创新点

• 采用模拟DFE实现均衡，相比数字DFE降低了功耗和复杂度。
• 使用了波特率CDR架构，能够在高损耗通道下实现稳定的时钟恢复。
• 在40nm CMOS工艺中实现了16Gb/s的数据率，并能在34dB损耗通道下工作，达到当时领先的通道损耗性能。

🏷 关键词

📄 原文摘要

Clemenz Portmann3, Neil Bulman1, Eugenia Cordero Crespo1, Peter Hearne1, Patty Huang3, Ben Kerr1, Pulkit Khandelwal1, Franz Kuhlmann2, Shaun Lytollis1, Joaquim Machado1, Casey Morrison2, Scott Morrison2, Shahriar Rabii3, Dushmantha Rajapaksha1, Vishnu Ravinuthula2, Giuseppe Surace1 1 Texas Instruments, Northampton, United Kingdom, Texas Instruments, Dallas, TX, 3 Arda Technologies, Mountain View, CA 2 In networking systems today data rates are increasing beyond 15Gb/s and yet the installed backplanes are made of low cost materials with losses in excess of 30dB at 7.5GHz. Standards, such as IEEE802.3ap-10GBASE-KR and OIFCEI25G, are specifying SerDes requirements for channels with 25dB loss at Nyquist and this has driven the development of SerDes with 4 or 5 tap DFEs [1]. Until now, solutions for 34dB or more channel loss have been limited to 10.3Gb/s or below [2,3], whereas this paper describes an adaptive 14-tap DFE

👥 作者与机构

Andrew K. Joy1, Hugh Mair2, Hae-Chang Lee3, Arnold Feldman3,