February 21, 2011 / 10:50 AM Beyond the Horizon: The Next 10x Reduction in Power - Challenges and Solutions 10:50AM The energy efficiency of electronic circuits has dramatically improved over the past two decades. At the same time, computation, storage, and communication demands continue to grow with emerging wireless multimedia devices. In this inaugural Plenary Technology-Roundtable event, experts will discuss the opportunities to achieve the next order-of-magnitude reduction in energy consumption across various domains, including analog, digital, RF, and memory. The line between analog and digital continues to blur, as analog circuits are enhanced by applying digital corrections to compensate for increased analog component variability with process scaling. As well, digital will incorporate more analog to become more adaptive; for example, to optimize operating voltages at a fine-grain to match workloads and process variations. Memory circuits will need

📋 论文概要

本文展望了未来十年实现10倍功耗降低的挑战与解决方案，强调系统级方法、位单元优化和低电压数字电路材料的重要性，并探讨了TSV、RF集成电感变压器以及协同设计CAD工具等关键方向。

💡 主要创新点

• 提出了系统级协同设计方法，将封装、架构、电源和天线一体化优化以实现能量效率最大化。
• 指出了TSV在降低I/O功耗和片上互连长度中的关键作用，以及低电阻集成电感变压器对RF电路的挑战。

🏷 关键词

📄 原文摘要

materials for low-voltage digital circuits. TSVs will be important in reducing I/O power and the length of on-chip interconnects. For RF, integrated inductors and transformers with significantly lower resistance will be the challenge. Future CAD tools optimizing energy will focus on co-design of packaging, architecture, power sources, and antenna to provide the best system solution. Domain experts will challenge the distinguished panelists to suggest directions and help create a roadmap for next-generation energy-efficient electronics. Moderator: Jan Rabaey University of California, Berkeley, Berkeley, CA Domain Experts: Mark Horowitz Stanford University, Palo Alto, CA Takayasu Sakurai University of Tokyo, Tokyo, Japan Jack Sun TSMC, Hsin-Chu, Taiwan Dan Dobberpuhl Consultant, Monterey, CA Kiyoo Itoh Hitachi, Tokyo, Japan Philippe Magarshack STMicroelectronics, Crolles, France Asad Abidi University of California,

👥 作者与机构

to use a system-level approach which requires bit-cell optimization, low-voltage operation with integrated regulators, 3D Through-Silicon Vias (TSV), and process optimization. RF transceivers will continue to trend toward highly-digital architectures., The role of process-technology innovation and CAD tools will also be discussed. Future process technology will deliver new transistor structures and higher-mobility channel