A 0.4-to-3GHz Digital PLL with Supply-Noise Cancellation Using Deterministic Background Calibration

📋 论文概要

该论文提出了一种0.4至3GHz的数字锁相环（DPLL），通过确定性后台校准技术实现电源噪声抑制，解决了传统DPLL中TDC量化误差与振荡器相位噪声之间的带宽折衷问题，从而在宽频率范围内降低抖动。

💡 主要创新点

• 提出了一种基于确定性后台校准的电源噪声消除技术，无需额外模拟电路即可有效抑制电源噪声对DPLL性能的影响。
• 通过数字环路滤波器的动态重构，实现了灵活的环路响应设置，优化了锁定行为并降低了抖动。

🏷 关键词

📄 原文摘要

viable alternative to classical charge-pump analog PLLs [1-4]. By obviating the need for a large loop filter capacitor and a high-performance charge pump, DPLLs offer area savings and easier scalability to newer processes. The ability to reconfigure the digital loop filter dynamically offers flexibility in setting the loop response and helps to optimize the locking behavior of the DPLL [1]. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise mandate either a high-resolution TDC or a low-noise oscillator to minimize jitter [2]. Further, much like in an analog PLL, the ring oscillator is susceptible to supply noise, which especially limits the jitter performance of a DPLL integrated into a large digital system. A low-dropout regulator is commonly used

👥 作者与机构

Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu

Oregon State University, Corvallis, OR Digital phase-locked loops (DPLLs) have recently emerged as a