A 4R2W Register File for a 2.3GHz Wire-Speed POWERTM Processor with Double-Pumped Write Operation

📋 论文概要

本文针对多端口寄存器文件面积随端口数量平方增长的问题，提出一种4读2写寄存器文件，采用双泵写入操作，在2.3GHz wire-speed POWER处理器中实现高带宽。通过减少物理写端口数量，有效降低了面积开销。

💡 主要创新点

• 采用双泵写入操作，在单个时钟周期内完成两次写操作，从而减少物理写端口数量，降低寄存器文件面积。
• 优化电路设计，支持4读2写操作，满足高频处理器多端口需求。

🏷 关键词

📄 原文摘要

Sherman M. Dance2, Sebastian Ehrenreich3, Bruce M. Fleischer1, Thomas W. Fox1, Kyle M. Holmes4, Junichi Mihara5, Yutaka Nakamura5, Shohji Onishi5, Robert Shearer2, Dieter Wendel6, Leland Chang1 1 IBM T. J. Watson Reseach Center, Yorktown Heights, NY, IBM Systems and Technology Group, Rochester, MN, 3 Hoerner & Sulger, Schwetzingen, Germany, 4 IBM Systems and Technology Group, Essex Junction, VT, 5 IBM Systems and Technology Group, Kyoto, Japan, 6 IBM Systems and Technology Group, Boeblingen, Germany 2 In multi-ported register files, memory cell size grows quadratically with the total number of ports due to wordline and bitline wiring. Reducing the number of physical access ports in a memory cell can thus lead to significant area and power savings as well as latency improvement. Double-pumped register files operate access ports twice in a single clock period to reduce area by halving the number of physical ports in the memory cell—a technique often confined to lowfrequency applications.

👥 作者与机构

Gary S. Ditlow1, Robert K. Montoye1, Salvatore N. Storino2,