← 返回论文列表 📄 下载原文 PDF  ISSCC 2011 · 10.7
ISSCC 2011Session 10 · NYQUIST-RATE CONVERTERSData Converters90nm CMOS

A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文提出了一种12位1.25GS/s的电流舵DAC,采用90nm CMOS工艺,通过优化电流源结构和开关驱动技术,在高达500MHz输入频率下实现了超过70dB的无杂散动态范围(SFDR),有效解决了高频动态失真问题。

💡 主要创新点

核心指标
12位分辨率,1.25GS/s采样率,SFDR >70dB @ 500MHz
工艺节点
90nm CMOS
重要性
发表年份
ISSCC 2011

🏷 关键词

电流舵DACSFDR高速DAC90nm CMOS

📄 原文摘要

The current-steering DACs are commonly used in generating high-frequency signals [1-4]. A current-steering DAC comprises current cells of various sizes. Each of them contains a current source and a current switch. The DAC static linearity, specified as differential nonlinearity (DNL) and integral nonlinearity (INL), is mainly determined by the mutual matching and the output resistance of the current sources. The DAC also exhibits dynamic distortion. It is manifested as spurious-free dynamic range (SFDR) degradation. The SFDR decreases rapidly with increasing input frequency. There are two major sources of dynamic distortion, code-dependent switching transients (CDST) and code-dependent output-loading variation (CDLV). Switching transients are temporal disturbances in DAC output when the current switches in current cells make transitions. The output loading of a DAC varies when the output impedances of current cells change due to

👥 作者与机构

Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu

National Chiao Tung University, Hsinchu, Taiwan

分类:Data Converters · 年份:ISSCC 2011