A Scalable Sub-1.2mW 300MHz-to-1.5GHz HostClock PLL for System-on-Chip in 32nm CMOS

📋 论文概要

提出一种适用于片上系统（SoC）主机时钟的超低功耗锁相环（PLL），工作在300MHz至1.5GHz频率范围，功耗低于1.2mW。该PLL采用32nm高k金属栅极逻辑CMOS工艺实现，具备工艺可扩展性，并能在工艺变化和最小电源电压下保持环路稳定，满足移动设备始终在线始终连接功能对低功耗的需求。

💡 主要创新点

• 采用低功耗架构和电路技术，实现sub-1.2mW的超低功耗，同时覆盖300MHz至1.5GHz的宽频率范围。
• 提出工艺可扩展的设计方法，确保PLL在下一代工艺节点下仍能保持系统响应和环路稳定性。
• 针对SoC的AOAC特性优化，在不牺牲性能的前提下实现低功耗与快速锁定的平衡。

🏷 关键词

📄 原文摘要

System-on-chips (SoCs) are being widely adopted in mobile applications, and are driven by the need for longer battery life, their power budget continues to decrease. In addition, the phase-locked loop (PLL) for the SoC host clock has to be a very low power circuit to support the always-on always-connected (AOAC) feature for SoCs integrated into hand-held devices. The proposed PLL, implemented in a high-k metal-gate 32nm logic CMOS technology, provides process scalability to the next process technology node, uncompromised system response, and loop stability under process variation and minimum power envelop constraints. As the jitter requirements for the host clocking PLL are not stringent, the proposed architecture emphasizes the power efficiency over the jitter performance. Figure 5.5.1 shows the architecture of the proposed PLL which includes a firstorder resistor-less loop filter (LF). The PLL consists of a current-controlled sawtooth-wave oscillator (CCO), a non-current-steering cha

👥 作者与机构

Hyung-Jin Lee, Alexandra M. Kern, Sami Hyvonen, Ian A. Young

Intel, Hillsboro, OR