⚡ 本页包含 AI 生成的分析内容，仅供参考
本文介绍了一款采用32nm CMOS工艺的Westmere-EX Xeon企业处理器，集成了10个核心和共享三级缓存。重点描述了通过独立核心电源门控和C6状态管理实现空闲功耗降低，以及高速I/O链路的鲁棒性优化，显著提升了每瓦性能。
of 10 Westmere 32nm cores [2] and a shared inclusive L3 cache (LLC) integrated on a monolithic die, with link-based I/Os. This paper focuses on the innovations and circuit optimizations over the predecessor [3] targeting idle power reduction, robust high-speed I/O links, and performance per watt improvements. The processor is implemented in 32nm CMOS using high-κ metal gate transistors and nine copper interconnect layers [4]. Core C6 power management is supported with individually controlled power gates for each of the 10 cores (Fig. 4.3.1). Core state is retained in a dedicated SRAM block, while the power gates are switched-off. Macro clock gating (MCG) is implemented in the uncore to reduce switching power from local clock network and associated logic. Power consumption in this state is limited to critical
Shankar Sawant, Utpal Desai, Gururaj Shamanna, Lokesh Sharma,
Mandar Ranade, Anil Agarwal, Sampath Dakshinamurthy, Rajagopal Narayanan Intel, Bangalore, India The next-generation enterprise Xeon® processor [1] consists