A 5.3GHz Digital-to-Time-Converter-Based Fractional-N All-Digital PLL

📋 论文概要

该论文提出了一种基于数字时间转换器(DTC)的全数字锁相环(ADPLL)架构，用于解决传统ADPLL带内杂散水平难以满足要求的问题。通过采用可扩展时间分辨率的DTC，实现了5.3GHz频率合成，并改善了杂散性能。

💡 主要创新点

• 提出了一种基于DTC的新型ADPLL架构，通过数字时间转换器替代传统时间数字转换器(TDC)，降低了带内杂散。
• 实现了时间分辨率的可扩展性，便于在不同工艺节点下优化性能。

🏷 关键词

📄 原文摘要

Advanced deep-submicron CMOS processes are well-suited for a digital implementation of phase-locked loop-(PLL) based frequency synthesizers. Recently, several RF all-digital phase-locked loops (ADPLL) have been reported [2,4,5]. While ADPLLs come close to achieving the phase-noise performance of analog PLLs, the in-band spur level requirement is still challenging. In this paper we present a new digital-to-time-converter-(DTC) based ADPLL architecture where the time resolution can be easily scaled. The block diagram of the DTC-based ADPLL is shown in Fig. 3.2.1. The ADPLL is operating in the true phase domain [1]. The ADPLL control loop updates the DCO frequency so that the DCO phase RDCO, measured by counting the DCO clock edge transitions, follows the reference phase RREF (RREF_i is integer and RREF_f is fractional part), produced by accumulating the frequency control word (FCW) on each reference clock cycle. The DTC is added to lower the quantization

👥 作者与机构

Nenad Pavlovic, Jos Bergervoet

NXP Semiconductors, Eindhoven, The Netherlands