A Low-Voltage 1Mb FeRAM in 0.13µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin in Scaled CMOS

📋 论文概要

本文提出了一种在0.13µm CMOS工艺中实现的1Mb低电压铁电存储器（FeRAM），采用时间数字转换（TDS）传感技术来扩大工作裕度，解决了FeRAM在先进工艺节点下位电荷减少和晶体管操作裕度不足的问题。该设计适用于低功耗便携设备如植入式医疗器件。

💡 主要创新点

• 采用时间数字转换（TDS）传感技术替代传统电压传感，在低电压下显著提升读取裕度和可靠性。
• 在0.13µm CMOS工艺中实现了1Mb容量的FeRAM，工作电压可低至1.0V以下，降低了访问能量。

🏷 关键词

📄 原文摘要

Massachusetts Institute of Technology, Cambridge, MA, Texas Instruments, Dallas, TX 2 Low-power portable electronics such as implantable medical devices require low-access-energy non-volatile memory to deliver longer battery lifetime and richer functionality. Ferroelectric random access memory (FeRAM) technology is a good candidate for both storage [1] and non-volatile RAM [2]. The power and supply voltage of FeRAM need further reduction, and this work presents a solution in anticipation of FeRAM scaling to advanced technology nodes for which the bitcell charge reduces and transistors operate at 1V and below. Specifically, a time-to-digital converter (TDC) sensing scheme is developed to capture the diminishing charge signal from the memory element at low supply voltage. The 1T1C cell in Fig. 11.6.1 based on the technology in [3] contains a ferroelectric capacitor that exhibits a hysteresis in stored charge versus bias VFE. During

👥 作者与机构

Masood Qazi1, Michael Clinton2, Steven Bartling2, Anantha P. Chandrakasan1