⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一款采用40nm CMOS工艺实现的4通道收发器，通过TX预加重、RX连续时间线性均衡器和判决反馈均衡器来补偿背板带宽限制，支持多标准数据速率，实现了8.4mW/Gb/s的能效和48Gb/s的总数据率。
Marcus Van Ierssel1, Afshin Rezayee2, Angus McLaren1, Chris Holdenried1, Jennifer Pham1, Eric So1, David Cassan1, Saman Sadr1 1 Snowbush-Gennum, Toronto, Canada, now with SecureKey, Toronto, Canada 2 The bandwidth limitation of existing backplanes has become an obstacle to meeting the increasing demand for high-data-rate wireline transmission. In order to compensate for this limitation, TX pre-emphasis, RX continuous-time linear equalizer (CTLE) and DFE are necessary [1,2]. This work presents a 4-lane transceiver implemented in 40nm CMOS technology that operates over a wide range of data rates from 1 to 12Gb/s (48Gb/s aggregated) using NRZ coding. The supply voltages are 0.9V and 1.8V. An algorithm is developed to adapt the CTLE and DFE to cancel the channel ISI. No inductors are used in the design and ring oscillators are used for both the TX and RX clock generation. This provides a wide frequency-tuning range, small layout area, and high design portability.
Mehrdad Ramezani1, Mohamed Abdalla1, Ayal Shoval1,