A 1.7mW 11b 1-1-1 MASH ΔΣ Time-to-Digital Converter

📋 论文概要

该论文提出了一种1.7mW、11位分辨率的1-1-1 MASH ΔΣ时间数字转换器(TDC)，采用基于松弛振荡器的结构。通过将参考电压与参考电流关联，使振荡器频率仅依赖于无源RC元件，从而显著提升了对工艺、电压和温度(PVT)变化的容忍性，并改善了级间匹配。

💡 主要创新点

• 提出基于松弛振荡器的1-1-1 MASH ΔΣ TDC架构，在低功耗下实现高分辨率。
• 通过关联VREF和IREF使振荡器频率仅取决于RC无源器件，增强了PVT稳定性。
• 采用MASH结构改善了传统ΔΣ TDC的级间匹配问题。

🏷 关键词

📄 原文摘要

SCK-CEN, Mol, Belgium 3 KH Kempen, Geel, Belgium The frequency of the relaxation oscillator can be expressed as IREF/(VREF·2C). By correlating VREF and IREF as VREF = IREF·R, its frequency becomes only dependant on passive components, that is, 1/(2·RC). Thus, it exhibits inherent PVT-variation tolerance and the matching between stages is better than for its MASH ADC counterparts. 1 2 Recently, high-resolution TDCs have gained more and more popularity due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs [1, 3], pipeline TDCs [2], and SAR TDCs [4]. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to achieve sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused

👥 作者与机构

Ying Cao1,2, Paul Leroux1,3, Wouter De Cock2, Michiel Steyaert1

KU Leuven, Leuven, Belgium