⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种数字宽带时钟数据恢复（CDR）架构，解决了传统数字CDR频率跟踪范围有限的问题，在40nm CMOS工艺下实现了8Gb/s数据率下±15.6kppm的频率跟踪能力。
Seong-Ho Lee1, Hamid Hatamkhani1, Mario Caresosa1, Karo Khanoyan1, Haitao Tong1, Duke Tran1, Anthony Brewster1, Ichiro Fujimori1 1 2 Broadcom, Irvine, CA Broadcom, Austin, TX It has been well understood that the digital clock and data recovery (CDR) architecture has many system merits over the analog counterpart for multi-Gb/s transceivers [1]. However, the applications have been limited in systems where the clock is forwarded or has small frequency offset [2, 3], due to the finite frequency and jitter tracking capability of the digitally controlled phase rotation. Recently, tracking range up to ±7800ppm has been reported [4] to extend the applications to the SATA/SAS interfaces that require 5000ppm spread spectrum clocking (SSC) to suppress electromagnetic emissions. To enable broad acceptance in high-speed applications, the digital CDRs must have much wider tracking range. First, it is highly desirable to use an on-chip (CMOS) clock available at any frequency Fref as the reference fo
Hui Pan1, Magesh Valliappan2, Wei Zhang1, Kambiz Vakilian1,