A 6.5mW Inductorless CMOS Frequency Divider-by-4 Operating up to 70GHz

📋 论文概要

该论文提出了一种无电感器的CMOS四分频器，工作频率高达70GHz，功耗仅为6.5mW。通过采用新型电路拓扑，解决了传统静态CML锁存器在毫米波频段功耗过大的问题。

💡 主要创新点

• 提出了一种无电感器的四分频器结构，避免了电感的使用，降低了芯片面积和成本。
• 实现了高达70GHz的工作频率，同时功耗仅为6.5mW，显著优于传统CML分频器。

🏷 关键词

📄 原文摘要

University of Pavia, Pavia, Italy, University of Modena e Reggio Emilia, Modena, Italy, 3 Istituto Universitario di Studi Superiori di Pavia, Pavia, Italy 2 With a cut-off frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding from Radio Frequency to mm-Waves applications. Frequency dividers are key building blocks for LO generation in wireless transceivers and clock synchronization in front-ends for wire-line and optical communications. Dividers based on traditional static CML latches work over a wide band but power dissipation at mm-Waves is extremely large. To save power, recently reported mm-Wave PLLs propose tunable narrowband dividers, based on injection-locking techniques, together with digital calibration algorithms [1,2]. On the other hand, for division factors higher than 2, the frequency locking range of injection-locked oscillators is very limited, mandating fine and frequent calibrations. This paper introduces clocked differential amplifiers,

👥 作者与机构

Andrea Ghilioni1, Ugo Decanis1, Enrico Monaco2,3, Andrea Mazzanti1,

Francesco Svelto1