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提出了一种采用数字后台DAC线性化技术的连续时间ΔΣ调制器，在8mW功耗和50MS/s采样率下实现了81dB SFDR，解决了多比特DAC非线性问题。
There is ongoing effort to realize low-power ΔΣ ADCs with more than 10MHz bandwidth (BW) – especially for wireless transceivers. Besides the trend to make these ADCs more reconfigurable [1], recent advances in the design of CT ΔΣ modulators focused on design improvements [2], on replacing analog by digital circuits [3, 4], or on avoiding costly multi-bit DACs with time-domain or singlebit feedback [1, 4]. Apart from that, the power versus performance advances in ΔΣ ADCs have slowed down, and the best FOM for above 10MHz ΔΣ modulators (ΔΣMs) is still 120fJ/conv [5]. Among other reasons, the further advance of ΔΣMs to higher conversion BWs with compatible FOM faces two hurdles: first, high BW requires a low OSR to achieve a feasible sampling frequency fS. Since the filter order rarely exceeds three, multi-bit operation is commonly employed. This requires linearization of the multilevel feedback DAC, e.g., by using DEM,
John G. Kauffman, Pascal Witte, Joachim Becker, Maurits Ortmanns
Ulm University, Ulm, Germany