A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values

📋 论文概要

该论文提出了一种工作在重复互补值上的AES电路，能够同时抵抗侧信道攻击和故障攻击。通过使用互补数据表示，该电路有效防止了通过功耗或电磁辐射提取密钥以及通过注入错误进行差分故障分析的安全威胁。

💡 主要创新点

• 首次提出利用重复互补值（Duplicated Complemented Values）技术同时防护侧信道和故障攻击，避免了传统单一对策的局限性。
• 在电路级实现了一种新的双轨互补逻辑风格，使功耗和电磁辐射与数据无关，同时检测并容忍单比特故障。

🏷 关键词

📄 原文摘要

Cryptographic circuits can be subjected to several kinds of side-channel and fault attacks in order to extract the secret key. Side-channel attacks can be carried by measuring either the power consumed or the EM waves emitted by the cryptographic module and trying to find a correlation between the given sidechannel and the data manipulated [1]. Concerning fault attacks, in the case of differential fault attacks (DFA) [2], a cryptographic calculation is corrupted in such a way as to retrieve information about the secret key. Faults can be induced by different means such as lasers, voltage glitches, electromagnetic perturbations or clock skews. Several counter-measures, like in [3], have been separately proposed to tackle either kind of attack. In this paper, we describe the implementation of an AES chip where duplicated a

👥 作者与机构

Marion Doulcier-Verdier1,2, Jean-Max Dutertre2, Jacques Fournier1,2,

Jean-Baptiste Rigaud2, Bruno Robisson1,2, Assia Tria1,2 1 2 CEA-LETI-MINATEC, Gardanne, France, Ecole Nationale Supérieure des Mines de Saint-Etienne, Gardanne, France