A 480mW 2.6GS/s 10b 65nm CMOS Time-Interleaved ADC with 48.5dB SNDR up to Nyquist

📋 论文概要

本文提出一款65nm CMOS工艺的64路时间交织10位ADC，采用分层交织架构和开环缓冲器阵列（前馈采样与反馈SAR模式），实现2.6GS/s采样率、48.5dB SNDR（奈奎斯特频率处），功耗仅480mW，解决了多通道电视频段数字化中低功耗高精度ADC的集成难题。

💡 主要创新点

• 提出64路时间交织架构，结合分层交织与开环缓冲器阵列，在反馈SAR模式下实现前馈采样，降低功耗并提升线性度。
• 集成片上校准技术，补偿通道间失配，在2.6GS/s下达到48.5dB SNDR。

🏷 关键词

📄 原文摘要

many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die [1] could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64× interleaved 2.6GS/s 10b 65nm CMOS ADC with on-chip calibrations, combining interleaving hierarchy with an open-loop buffer array operated in feedforwardsampling and feedback-SAR mode. The ADC achieves an SNDR of 48.5dB at Nyquist and consumes only 0.48W. Time-interleaving of multiple low-rate SAR ADCs, e.g., 64 or more, offers power efficiency but so far has been limited to low resolutions [4]. At 10b level, flat interleaving for that many units, i.e., one T/H per ADC, requires an input buffer

👥 作者与机构

Kostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard Van der Weide

NXP Semiconductors, Eindhoven, The Netherlands Trends in cable TV reception for data and video require simultaneous capture of