A 56GS/s 6b DAC in 65nm CMOS with 256×6b Memory

📋 论文概要

该论文实现了一款采用65nm CMOS工艺的56GS/s 6位电流舵数模转换器（DAC），并集成了256×6位片上存储器。针对光通信系统中高速DSP SoC集成的挑战，该DAC以低功耗小面积实现了超高采样率，解决了CMOS DAC此前速度受限的问题。

💡 主要创新点

• 采用新型高速架构和电路技术，在65nm CMOS中实现了56GS/s的6位DAC，远超当时CMOS DAC的常规速度。
• 集成256×6位片上存储器，支持高数据率下的多通道并行操作，降低了系统接口复杂度。
• 通过优化电流源和开关设计，在保持6位精度的同时实现了极低功耗和紧凑面积。

🏷 关键词

📄 原文摘要

Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan Ciena, Ottawa, Canada Modern optical systems increasingly rely on DSP techniques for data transmission at 40Gbs and recently at 100Gbs and above. A significant challenge towards CMOS TX DSP SoC integration is due to requirements for four 6b DACs (Fig. 10.8.1) to operate at 56Gs/s with low power and small footprint. To date, the highest sampling rate of 43Gs/s 6b DAC is reported in SiGe BiCMOS process [1]. CMOS DAC implementations are constraint to 12Gs/s with the output signal frequency limited to 1.5GHz [2-4]. This paper demonstrates more than one order of magnitude improvement in 6b CMOS DAC design with a test circuit operating at 56Gs/s, achieving SFDR >30dBc and ENOB>4.3b up to the output frequency of 26.9GHz. Total power dissipation is less than 750mW and the core DAC die

👥 作者与机构

Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang,