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该论文在65nm低功耗部分耗尽SOI (LP PD-SOI) 和传统低功耗体硅 (LP Bulk) 工艺上实现了相同的LDPC编解码器电路，并进行公平比较。结果表明PD-SOI能够在相同电压下提高最大频率，或在相同频率下降低动态功耗，并通过针对PD-SOI优化的数字电源切换技术进一步改善性能。
Alexandre Valentian2, Marc Belleville2, Christine Raynaud1, Damien Croain1, Pascal Urard1 1 STMicroelectronics, Crolles, France, CEA-LETI-MINATEC, Grenoble, France 2 A Low-Density Parity-Check (LDPC) codec circuit is implemented in a 65nm Low-Power Partially-Depleted SOI (LP PD-SOI) technology, as well as in a “conventional” Low-Power Bulk technology for a fair comparison. PD-SOI allows to increase maximum frequency versus bulk at a given voltage, and to decrease dynamic power versus bulk at a given frequency. Thanks to a digital powerswitching technique specifically optimized for LP PD-SOI, we demonstrate a leakage current reduction versus bulk 65nm LP implementation, solving one of the most critical problems of PD-SOI technology, as identified in previous publications. This LDPC codec supports the 12 modes required by the 802.11n standard (Wifi): 4 code rates (1/2, 2/3, 3/4, 5/6) over 3 possible block sizes (648, 1296
Julien Le Coz1, Philippe Flatresse1, Sylvain Engels1,