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该论文提出了一种在65nm CMOS工艺下实现的紧凑型60GHz功率放大器，能够在1V电源电压下输出18.6dBm的功率，解决了毫米波频段高路径损耗和低电源电压下功率合成效率的挑战。通过采用空间功率合成技术，满足了IEEE 802.15.3c标准中OFDM模式对峰值功率和可靠性的要求。
One of the remaining challenges in implementing CMOS 60GHz radios is to cover longer communication distance as the high path loss at mm-Wave frequencies demands higher EIRP, which in turn requires considerable design effort on the transmitter. In addition, to comply with the OFDM transmitting mode of the IEEE 802.15.3c standards, the power amplifier (PA) must be capable to handle a peak power level 6~9dB higher than the average without sacrificing reliability. With the low supply voltage limitation of deeply scaled CMOS technologies, efficient power-combining techniques are essential. Spatial power combining is an attractive solution to meet the EIRP goal, but at the cost of spending extra power on the complex signal distribution and in order to compensate for the phase-shifter loss. Spatial power-combining solutions also occupy larger area due to the requirement of multiple antennas, minimum antenna spacing,
Jiashu Chen, Ali M Niknejad
University of California, Berkeley, CA