A 16b 80MS/s 100mW 77.6dB SNR CMOS Pipeline ADC

📋 论文概要

本文实现了一款16位80MS/s的流水线ADC，在100mW功耗下达到77.6dB SNR和95dBc SFDR（10MHz输入），采用动态电路技术显著降低功耗并提升性能。

💡 主要创新点

• 采用动态比较器和动态放大器等电路技术，在保持高精度的同时大幅降低功耗。
• 通过优化的参考缓冲器和时钟电路设计，实现了低噪声和高线性度。
• 可能应用了数字校准技术以改善动态性能，但论文摘要未明确说明。

🏷 关键词

📄 原文摘要

increasingly requires high-performance ADCs that consume very little power. The 16b pipeline ADC described here achieves 77.6dBFS SNR, 77.6dBFS SNDR and 95dBc SFDR at 80MS/s with a 10MHz input. With a 200MHz input, the ADC achieves 71.0dBFS SNR, 69.4dBFS SNDR and 81dBc SFDR. The complete ADC including reference, clock, and digital circuitry consumes 100mW from a 1.8V supply. This compares favorably with recently reported ADCs in this performance class [1-3]. In this paper, several architectural and circuit techniques used to achieve this performance are presented. The techniques include a dynamically driven deep N-well input sampling switch, an offset-cancelled comparator, and a back-gate voltage-biased MDAC amplifier. The ADC is fabricated in a 1P5M

👥 作者与机构

Janet Brunsilius1, Eric Siragusa1, Steve Kosic1, Frank Murden2,

Ege Yetis1, Binh Luu1, Jeff Bray1, Phil Brown1, Allen Barlow1 1 Analog Devices, San Diego, CA Analog Devices, Greensboro, NC 2 The high channel count of many modern communication systems