A 570fsrms Integrated-Jitter Ring-VCO-Based 1.21GHz PLL with Hybrid Loop

📋 论文概要

本文提出了一种基于环形VCO的混合环路PLL，实现了570fsrms的集成抖动和1.21GHz的输出频率。通过宽环路带宽和低带内噪声设计，有效抑制了环形VCO的相位噪声，解决了全数字PLL中TDC量化误差导致带内噪声过高的问题。

💡 主要创新点

• 采用混合环路架构，结合模拟和数字技术，在保持环形VCO面积效率的同时显著降低抖动。
• 通过优化环路带宽和噪声抑制，实现了与LC VCO相当的抖动性能，但面积更小。

🏷 关键词

📄 原文摘要

Sampling clock jitter significantly degrades the circuit performance and dynamic range of an ADC [1]. This paper presents a 570fsrms integrated-jitter 1.21GHz PLL with a hybrid loop. A ring VCO has a much inferior phase noise characteristic as compared to an LC VCO, but its area efficiency is attractive. To suppress the phase noise of a ring VCO, a wide-loop-bandwidth PLL with sufficiently low in-band noise is indispensable. An all-digital PLL (ADPLL) [2] has insufficiently low in-band phase noise because of the quantization error of the time-to-digital converter (TDC) without employing additional techniques such as power-hungry time amplification [3]. On the other hand, a conventional analog PLL has a superior in-band phase noise but needs a large loop-filter capacitor to maintain a wide tuning range due to a high control sensitivity of the ring VCO. The dual-tuning topology is useful for minimizing the size of the loop filter while maintaining

👥 作者与机构

Akihide Sai, Takafumi Yamaji, Tetsuro Itakura

Toshiba, Kawasaki, Japan