A 28nm High-Density 6T SRAM with Optimized Peripheral-Assist Circuits for Operation Down to 0.6V

📋 论文概要

本文提出一种28nm高密度6T SRAM，通过优化外围辅助电路（包括写辅助和读辅助），实现了在低至0.6V电源电压下的可靠工作，解决了工艺缩放导致的低电压SRAM稳定性问题。

💡 主要创新点

• 优化了外围辅助电路设计，包括写辅助和读辅助电路，提升了低电压下SRAM的读写稳定性。
• 在28nm工艺中实现了高密度6T SRAM单元与辅助电路的协同设计，支持0.6V超低压操作。

🏷 关键词

📄 原文摘要

Massachusetts Institute of Technology, Cambridge, MA, Texas Instruments, Dallas, TX An increasing amount of embedded memory is used in today’s ICs and consequently the design of low-power, high-density SRAM is becoming critical. With technology scaling, it is becoming increasingly more challenging to achieve reliable low voltage operation for SRAMs due to process variation. Recent work proposed various design innovations to address this problem [1-2]. Conventional 6T SRAM bit-cell provides high area density but fails to operate as supply voltage scales down. Instead, the work in [3] utilizes an asymmetrical 6T bit-cell that can operate down to 0.7V in 45nm CMOS. An alternative 8T bit-cell topology can potentially operate at lower Vmin [4-5], yet it leads to ~40% larger bit-cell area and suffers from half-select problem if used in a column-interleaved architecture. In this work, we present a 28nm high-density 6T SRAM operating

👥 作者与机构

Mahmut E. Sinangil1, Hugh Mair2, Anantha P. Chandrakasan1, 1