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ISSCC 2011Session 8 · ARCHITECTURES & CIRCUITS FOR NEXT GENERATION WIRELINE TRANSCEIVERSWireline I/O65nm CMOS

Gb/s CMOS SONET-Compliant Transceiver for Both RZ and NRZ Applications

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📋 论文概要

该论文提出了一款11.3Gb/s的CMOS SONET兼容收发器,同时支持RZ和NRZ数据格式。发送器驱动实现了17ps的上升/下降时间,接收器具有多级垂直阈值调整电路,实现了5mVpp-diff的输入灵敏度和0.54UI的抖动容限。芯片在65nm CMOS工艺下核心面积为1.36mm²,功耗为214mW。

💡 主要创新点

核心指标
11.3 Gb/s, 214mW, 1.36mm^2
工艺节点
65nm CMOS
重要性
发表年份
ISSCC 2011

🏷 关键词

SONET兼容RZ/NRZ收发器65nm CMOS低功耗

📄 原文摘要

Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz Broadcom, Irvine, CA An 11.3Gb/s CMOS SONET-compliant transceiver is designed to work in both RZ and NRZ data formats. The TX driver exhibits 17ps rise/fall times, 0.25psrms RJ, and 2pspp DJ. The RX has a multi-stage vertical threshold adjustment circuit. It achieves 5mVpp-diff RX input sensitivity with 0.54UI jitter tolerance. The transceiver core area occupies 1.36mm2 in 65nm CMOS and consumes 214mW. Two main data formats are widely deployed in optical networks: return to zero (RZ) and non-return to zero (NRZ). The RZ data format sends full-rate clock during “1”, while stays low during “0” (Fig. 8.1.1). This is equal to transmitting pulses at half baud period, i.e., 50ps for 10Gb/s operation. Transmitting narrower pulses in RZ signaling compensates pulse widening caused by dispersion in

👥 作者与机构

Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui,

分类:Wireline I/O · 年份:ISSCC 2011