A 0.024mm2 8b 400MS/s SAR ADC with 2b/Cycle and Resistive DAC in 65nm CMOS

📋 论文概要

该论文提出了一种在65nm CMOS工艺下实现的8位400MS/s逐次逼近型模数转换器，采用2位/周期转换和电阻型DAC架构，以解决传统SAR ADC速度受限的问题，实现了高转换速率和低功耗。

💡 主要创新点

• 采用2位/周期转换技术，通过插值采样减少转换周期数，提升转换速度。
• 使用电阻型DAC替代传统电容型DAC，降低功耗并提高线性度。

🏷 关键词

📄 原文摘要

Italy 2 The successive-approximation (SA) algorithm is traditionally used for lowbandwidth applications because it requires n clock cycles or more to obtain nbit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions [1]. This design uses the successive-approximation method to obtain 8b up to 400MS/s with very low power using a 1.2V supply. Key features of the architecture are a resistive DAC and a 2b-per-cycle conversion with interpolated sampling front-ends and shift registers. A cross-coupled bootstrapping network is also implemented to alleviate the signal-dependent clock feed-through. The very compact layout leads to a

👥 作者与机构

Hegong Wei1, Chi-Hang Chan1, U-Fat Chio1, Sai-Weng Sin1,

Seng-Pan U1, Rui Martins1,2, Franco Maloberti3 1 University of Macau, Macau, China Instituto Superior Tecnico, Lisbon, Portugal 3 University of Pavia, Pavia,