A 40Gb/s TX and RX Chip Set in 65nm CMOS

📋 论文概要

该论文提出了一款采用65nm CMOS工艺的40Gb/s发射机和接收机芯片组，旨在解决下一代光/电通信中高速收发器面临的带宽不足和高功耗问题。针对基于FIR的前馈均衡器因触发器时钟到Q延迟过大导致的性能退化，以及传统判决反馈均衡器的速度限制，论文提出了新的电路架构和设计方法。

💡 主要创新点

• 提出了一种克服触发器时钟到Q延迟影响的FFE架构，可能采用无源延迟元件与可调技术结合，以应对PVT变化。
• 针对DFE的速度限制，设计了新型高速反馈路径或改进的判决反馈均衡器结构。
• 在65nm CMOS工艺下实现了40Gb/s的全双工收发器，兼顾了功耗和面积效率。

🏷 关键词

📄 原文摘要

Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth and high power consumption. One major difficulty arises from the performance degradation of FIR-based FFEs as the FF’s CK-Q delay becomes significant to one bit period. Using passive components as delay elements [1][2] can relax this issue to some extent, but the untunable delay is quite vulnerable to PVT variations. Traditional DFEs also suffer from speed limitation in its feedback loop, and parallelization schemes usually introduce complex circuits and high power consumption. This paper presents a full-rate 40Gb/s transceiver prototype significantly alleviating the above issues. Figure 8.3.1 shows the transmitter, which consists of a 20GHz PLL, a 5-tap FFE with tunable delay, and a 1UI delay generator. To create exactly 1-bit delay, conventional FFE approach needs flip-

👥 作者与机构

Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

National Taiwan University, Taipei, Taiwan