A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140µW

📋 论文概要

该论文提出了一种适用于高分辨率低功耗传感器系统的三阶ΔΣ调制器，通过单运算放大器架构和电阻分压DAC实现了84dB SNDR和100kHz带宽，功耗仅140µW。解决了电阻梯度误差和高阶失真问题，无需数字校准或动态元件匹配。

💡 主要创新点

• 采用单运算放大器实现三阶ΔΣ调制器，显著降低功耗。
• 使用单个电阻分压器生成32个差分5位参考电压，并完全消除电阻梯度误差。
• 通过优化电阻尺寸和布局抑制高阶失真，实现96dB SFDR，无需数字校准或动态元件匹配。

🏷 关键词

📄 原文摘要

This third-order ΔΣ modulator [1, 2], suitable for high-resolution low-power sensor systems, consumes 140µW to obtain 84dB SNDR with OSR=16 and 100kHz signal bandwidth. The achieved FoM is 54fJ/conversion-step The DACs use a single resistive divider to generate 32 differential 5b reference voltages. The proposed scheme totally cancels the error caused by gradient in the resistance values. Resistor sizes and layout of the resistive DAC limit the high-order distortion terms and obtain an SFDR of 96dB at –4dBFS without the need for digital calibration or dynamic element matching (DEM). The scheme uses a second-order architecture with delays in its integrators to obtain a third-order noise shaping. This is thanks to an auxiliary block that injects (1-z-1)εQ (εQ is the quantization error) at the input of the second integrator of the second-order delta-sigma modulator, as shown in Fig. 27.5.1. The gain

👥 作者与机构

Aldo Pena Perez, Edoardo Bonizzoni, Franco Maloberti

University of Pavia, Pavia, Italy