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ISSCC 2011Session 5 · PLLsClocking & PLLs65nm CMOS

A Rotary-Traveling-Wave-Oscillator-Based AllDigital PLL with a 32-Phase Embedded Phase-toDigital Converter in 65nm CMOS

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📋 论文概要

本文提出了一种基于旋转行波振荡器(RTWO)的全数字锁相环(ADPLL),并集成了一个32相嵌入式相位-数字转换器。该架构避免了传统TDC所需的复杂电路和校准,简化了系统设计。

💡 主要创新点

工艺节点
65nm CMOS
重要性
发表年份
ISSCC 2011

🏷 关键词

全数字锁相环旋转行波振荡器相位-数字转换器

📄 原文摘要

more popular as possible alternatives to conventional analog charge-pump-based PLLs [1]. Currently, most of the ADPLLs are based on a time-to-digital converter (TDC) utilizing inverter delay chains. There have been tremendous efforts to improve TDC performance, i.e., maximizing resolution and reducing power consumption, but they normally require additional complex circuits. Recently, the ring-oscillator-based ADPLLs have been presented in [2, 3], which substantially simplify the architecture of ADPLL by eliminating inverter delay chains as well as calibration routines for period normalization that are required for the conventional TDC-based approach. However, due to the poor phase noise of the ring oscillators and the limited time resolution available from inverters,

👥 作者与机构

Koji Takinami, Richard Strandberg, Paul C. P. Liang,

Gregoire Le Grand de Mercey, Tony Wong, Mahnaz Hassibi Panasonic, Cupertino, CA All-digital phase-locked loops (ADPLLs) have recently become

分类:Clocking & PLLs · 年份:ISSCC 2011