⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种在65nm CMOS工艺下、0.5V供电的直流耦合神经信号采集芯片，面积仅0.013mm²，功耗5µW。通过消除交流耦合电容并采用低电压模拟设计，解决了传统神经接口面积大、功耗高、可编程性有限的问题。
interfaces has provided hope for patients with spinal-cord injuries, Parkinson’s disease, and other debilitating neurological conditions [1], and has boosted interest in electronic recording of cortical signals. State-of-the-art recording solutions [2-5] rely heavily on analog techniques at relatively high supply voltages to perform signal conditioning and filtering, leading to large silicon area and limited programmability. We present a neural interface in 65nm CMOS and operating at a 0.5V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller. These results are achieved by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic. The use of 65nm CMOS eases integration with low-power digital systems, while the low supply
Rikky Muller1, Simone Gambini1,2, Jan M. Rabaey1, 1
University of California, Berkeley, CA, 2Telegent Systems, Sunnyvale, CA Recent success in brain-machine