A Programmable Adaptive Phase-Shifting PLL for Clock Data Compensation Under Resonant Supply Noise

📋 论文概要

该论文提出了一种可编程自适应移相锁相环，用于在谐振电源噪声下补偿时钟数据。通过自适应调整时钟相位，有效缓解了电源噪声对高性能微处理器性能的影响。

💡 主要创新点

• 提出了一种可编程自适应移相PLL架构，能够动态补偿谐振电源噪声引起的时钟抖动。
• 实现了对40MHz至300MHz频段谐振噪声的自适应相位调整，提升了系统可靠性。

🏷 关键词

📄 原文摘要

Power supply noise has become one of the main performance-limiting factors in sub-1V technologies. Resonant supply noise caused by the package/bonding inductance and on-die capacitance has been reported as the dominant supply noise component in high performance microprocessors [1,2]. Resonant noise frequency typically resides in the 40MHz to 300MHz frequency band but can be made as low as 7MHz with a dedicated metal-insulator-metal capacitor technology [3]. Recently, adaptive clocking schemes have been proposed to mitigate the impact of resonant noise on circuit performance. Here, the clock period is intentionally modulated by the resonant noise such that the increased clock period partially compensates for the increased datapath delay, which is also modulated by the resonant noise. Figure 15.5.1 (top) illustrates the concept of the adaptive clocking scheme. In a “constant-period clock” scenario, sampling failures can occur

👥 作者与机构

Dong Jiao, Chris H. Kim

University of Minnesota, Minneapolis, MN