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ISSCC 2011Session 11 · NON-VOLATILE MEMORY SOLUTIONSMemory20nm

A 7MB/s 64Gb 3-Bit/Cell DDR NAND Flash Memory in 20nm-Node Technology

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📋 论文概要

本文介绍了一款采用20nm工艺的64Gb 3位/单元DDR NAND闪存芯片,实现了7MB/s的写入速度。该芯片满足了市场从2位/单元向3位/单元过渡的需求,解决了高密度存储下的可靠性和性能挑战。

💡 主要创新点

核心指标
7MB/s写入速度, 64Gb容量
工艺节点
20nm
重要性
发表年份
ISSCC 2011

🏷 关键词

3位/单元NAND闪存20nm工艺DDR接口高密度存储

📄 原文摘要

In-Mo Kim, Bo-Geun Kim, Min-Seok Kim, Yoon-Hee Choi, Seung-Hwan Shin, Youngson Song, Joo-Yong Park, Jae-Eun Lee, Chang-Gyu Eun, Ho-Chul Lee, Hyeong-Jun Kim, Jun-Hee Lee, Jong-Young Kim, Tae-Min Kweon, Hyun-Jun Yoon, Taehyun Kim, Dong-Kyo Shim, Jongsun Sel, Ji-Yeon Shin, Pansuk Kwak, Jin-Man Han, Keon-Soo Kim, Sungsoo Lee, Young-Ho Lim, Tae-Sung Jung Samsung Electronics, Hwasung, Korea Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require costeffective flash memory. To further expand the 3b/cell market, high write and read performances are essential [1]. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increases cell-to-cell interference and disturbance. We present a

👥 作者与机构

Ki-Tae Park, Ohsuk Kwon, Sangyong Yoon, Myung-Hoon Choi,

分类:Memory · 年份:ISSCC 2011