A 4.6GHz MDLL with -46dBc Reference Spur and Aperture Position Tuning

📋 论文概要

本文提出了一种4.6GHz的乘性延迟锁定环（MDLL），通过创新的孔径位置调谐技术（Aperture Position Tuning）精确对齐参考时钟边沿与VCO反馈边沿，有效抑制了参考杂散，实现了-46dBc的低参考杂散性能。该设计解决了MDLL中因时序失配或电荷泵偏移导致的相位误差问题。

💡 主要创新点

• 提出孔径位置调谐技术，通过调整参考边沿注入时刻来补偿环路中的时序失配和电荷泵偏移，从而降低相位误差。
• 在4.6GHz工作频率下实现了-46dBc的参考杂散，显著优于传统MDLL设计。

🏷 关键词

📄 原文摘要

University of California, Los Angeles, CA, Oracle, Menlo Park, CA 2 Multiplying delay-locked loops (MDLLs) [1-5] have been shown to have improved jitter accumulation and tracking over VCO-based PLLs. By injecting the reference clock edge into the VCO at each reference cycle, an MDLL removes the accumulated jitter of the VCO. The principal challenge in MDLL design is to align the injected reference edge with the loop feedback signal. Timing mismatch between the reference edge and the VCO feedback edge, or offsets in the charge pump, would introduce a phase error in the injected edge. The error manifests as a period jitter or reference spur in the frequency domain. This effect limits the minimum jitter attained by the MDLL. In previously published techniques [1-5], a select logic block generates an SEL pulse to briefly open an aperture for reference injection. A necessary attribute of the SEL pulse is that it is sufficiently sharp and well-positioned to select the next

👥 作者与机构

Tamer A. Ali1,2, Amr A. Hafez1, Robert Drost, Ronald Ho2, Chih-Kong Ken Yang1