A 21.7-to-27.8GHz 2.6-Degrees-rms 40mW Frequency Synthesizer in 45nm CMOS for mm-Wave Communication Applications

📋 论文概要

本文提出一款工作于21.7-27.8GHz的频率合成器，采用45nm CMOS工艺，实现了24.8%的调谐范围和2.57°rms的残余相位调制，功耗仅40mW。该合成器与倍频器和分频器结合，为IEEE 802.15.3c 60GHz通信标准提供所需的本振频率。

💡 主要创新点

• 在45nm CMOS工艺中实现了覆盖21.7-27.8GHz的宽调谐范围（24.8%），同时保持低功耗（40mW）和低相位噪声（2.57°rms）。
• 采用滑动中频结构，结合倍频器和二分频器，从单个PLL直接生成60GHz通信所需的四个本振频率。

🏷 关键词

📄 原文摘要

2 NXP Semiconductors, Eindhoven, The Netherlands, NXP Semiconductors, San Diego, CA This work presents a 21.7-to-27.8GHz frequency synthesizer in a 45nm CMOS process that combines a tuning range of 24.8%, a residual phase modulation of 2.57°rms (with integrated phase noise from 100kHz to 100MHz), and a total power dissipation of 40mW. Combined with a frequency multiplier-by-two circuit and a divider-by-two circuit in a sliding-IF configuration, the PLL provides the four source frequencies required by the IEEE 802.15.3c 60GHz communication standard. In addition, the attained phase noise makes it suitable for microwave links with higher-order modulation schemes used as the back-bone for 3G/LTE base-station networks. The PLL diagram is shown in Fig. 16.1.1. It consists of a PFD supplied by a 1.1V source, a programmable charge pump (CP) supplied with 1.8V, an external loop filter, a negative-gm VCO, a fixed prescaler, a chain of 2/3-dividers and two

👥 作者与机构

Juan F. Osorio1, Cicero S. Vaucher1, Bill Huff2, Edwin v.d. Heijden1, Anton de Graauw1