A Pattern-Guided Adaptive Equalizer in 65nm CMOS

📋 论文概要

本文提出了一种基于模式引导的自适应均衡器，采用65nm CMOS工艺实现。该均衡器通过检测特定数据模式来指导自适应算法，解决了高速率下信道恶化导致的均衡问题，相比传统非数据辅助方案具有更低的功耗和面积。

💡 主要创新点

• 提出模式引导的自适应均衡算法，利用特定5位模式检测来调整均衡器参数，避免了传统频谱平衡方法的复杂性。
• 在65nm CMOS工艺中实现了低功耗、小面积的自适应均衡器，适用于高速收发器。

🏷 关键词

📄 原文摘要

receivers is becoming a necessity as the data rates increase without channel improvements. Adaptive equalizers can be implemented using data-aided or non-data-aided schemes [1], with the latter requiring less area and power. Previous non-data-aided adaptive schemes [2-3] implement an asynchronous analog algorithm where the power spectrum of the received signal is checked for balance around a threshold frequency. Similarly, [4] proposes a digital adaptive algorithm which is based on the detection of specific 5-bit patterns. In all three works [2-4], however, adaptation is provided only for equalizers with a single coefficient, which are suitable for well-behaved channels. In contrast, this paper presents a digital adaptive engine for an equalizer with two coefficients: one adjusting the equalizer gain at

👥 作者与机构

Shayan Shahramian1, Clifford Ting1, Ali Sheikholeslami1,

Hirotaka Tamura2, Masaya Kibune2 1 University of Toronto, Toronto, Canada, Fujitsu Laboratories, Kawasaki, Japan 2 The use of adaptive equalizers at the front end of