Spur-Free All-Digital PLL in 65nm for Mobile Phones

📋 论文概要

该论文提出了一种用于手机的无杂散全数字锁相环（ADPLL），采用65nm CMOS工艺。它解决了数字控制振荡器（DCO）和时间数字转换器（TDC）量化导致杂散和相位噪声的问题。

💡 主要创新点

• 提出了抑制DCO有限步长引起的远区杂散和相位噪声的技术
• 改进了TDC分辨率以降低近整数N信道的数据调制和频谱掩模失真

🏷 关键词

📄 原文摘要

all-digital PLL (ADPLL) [1] for Bluetooth radios has proven benefits of CMOS scaling and integration, demonstrators for more challenging wireless standards have emerged [2-6]. In the ADPLL, however, the digitallycontrolled oscillator (DCO) and time-to-digital converter (TDC) quantize the time and frequency tuning functions, respectively, which can lead to spurious tones and phase noise increase. As such, finite TDC resolution can distort data modulation and spectral mask at near integer-N channels, while finite DCO step size can add far-out spurs and phase noise. Also, a major underreported issue is an injection pulling of the DCO due to harmonics of the digital activity at closelyspaced frequencies, which can also create spurs. This work addresses all these

👥 作者与机构

Robert Bogdan Staszewski1, Khurram Waheed2, Sudheer Vemulapalli2,

Fikret Dulger2, John Wallberg2, Chih-Ming Hung2, Oren Eliezer2 1 Delft University of Technology, Delft, The Netherlands, Texas Instruments, Dallas, TX 2 After the first-ever