Clock Generation for a 32nm Server Processor with Scalable Cores

📋 论文概要

该论文针对多核服务器处理器中核间数据吞吐量和延迟问题，提出了一种低功耗、低抖动、高数据吞吐量和低延迟的时钟生成系统，并在32nm CMOS工艺中实现。

💡 主要创新点

• 采用低功耗低抖动时钟分配网络，减少核间时钟偏差。
• 针对可扩展核心的时钟同步架构，支持高数据吞吐量和低延迟。
• 基于32nm工艺优化时钟生成电路，降低功耗同时提升性能。

🏷 关键词

📄 原文摘要

Intel, Santa Clara, CA Within a given power envelope, the performance of a multi-core enterprise processor is greatly affected by inter-core (including I/O) data throughput and data transport latency. This paper presents the implementation of a clock system targeting low-power low-skew high-data throughput and low latency for a nextgeneration Xeon® server processor [1,2] with scalable cores in a 32nm 9-metal digital CMOS process. Figure 4.7.1 is the die diagram of the processor featuring 8 SandyBridge cores

👥 作者与机构

Shenggao Li, Ashwin Krishnakumar, Edward Helder, Roan Nicholson, Vivian Jia