A TDC-less 7mW 2.5Gb/s Digital CDR with Linear Loop Dynamics and Offset-Free Data Recovery

📋 论文概要

该论文提出了一种无时间数字转换器(TDC)的数字时钟数据恢复(CDR)电路，采用线性环路动态和无偏移数据恢复技术，实现了2.5Gb/s的数据速率和7mW的低功耗，解决了传统模拟环路滤波器大电容难以集成的问题。

💡 主要创新点

• 提出无TDC的数字CDR架构，避免了TDC的非线性和量化噪声
• 实现线性环路动态，改善了环路稳定性和抖动性能
• 实现无偏移数据恢复，消除了数据恢复中的直流偏移误差

🏷 关键词

📄 原文摘要

A clock and data recovery (CDR) circuit is the key building block in all serial communication systems. A classical CDR is implemented using a Type-2 phaselocked loop (PLL) wherein a passive lead-lag analog loop filter is used to set the loop response. Large capacitors needed to achieve low jitter transfer bandwidth and a highly over-damped response to reduce jitter peaking prohibit monolithic integration of the analog loop filter [1, 2]. Digital loop filters (DLFs) that are robust to process and temperature variations have recently emerged as an alternate solution to implementing fully integrated CDRs [3-5]. A bang-bang phase detector provides a simple interface to the DLF without any inherent static phase offset (SPO) [1, 3]. However, it introduces a large phase quantization error that limits the jitter transfer bandwidth, and its nonlinear behavior makes loop dynamics difficult to control. A time-to-digital converter

👥 作者与机构

Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu

Oregon State University, Corvallis, OR