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ISSCC 2012Session 24 · 10GBASE-T & OPTICAL FRONTENDSWireline I/O90nm CMOS

25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-Based Optical Links in 90nm CMOS

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文在90nm CMOS工艺中实现了两种基于VCSEL的多模光纤光链路,分别达到25Gb/s 3.6pJ/b和15Gb/s 1.37pJ/b的能效,解决了高性能计算系统对亚2pJ/bit能效光互连的需求。通过共享发射机并采用两种不同接收机,探索了功耗、带宽和面积之间的权衡。

💡 主要创新点

核心指标
25Gb/s @ 3.6pJ/b, 15Gb/s @ 1.37pJ/b
工艺节点
90nm CMOS
重要性
发表年份
ISSCC 2012

🏷 关键词

VCSEL光互连低功耗CMOS多模光纤

📄 原文摘要

Future high-performance computing systems require sub-2pJ/bit power efficiencies at >10Gb/s [1-2]. The best reported optical link efficiencies at these data rates are ≥2.5pJ/bit [1-4]. This paper describes two VCSEL-based multimode (MM) fiber optical links achieving sub-2pJ/bit power efficiency from 15Gb/s to 22Gb/s. The links realized in 90nm CMOS share the same TX but use two different RXs that explore different aspects of the power/BW/area tradeoff. The system-level block diagram of the optical link and the TX circuits are shown in Fig. 24.5.1. The laser diode driver (LDD) TX consists of a 2-stage preamplifier and a main driver stage (DRV). The preamplifier stages are Cherry-Hooper (CH) amplifiers with 1.6V supply VDD_PA. The DRV is an inductively-peaked differential amplifier, one side wire-bonded to a 5µm diameter 850nm GaAs laser diode (VCSEL) [5] and the other side terminated to 60Ω on chip. The DRV is

👥 作者与机构

Jonathan Proesel, Clint Schow, Alexander Rylyakov

IBM T. J. Watson, Yorktown Heights, NY

分类:Wireline I/O · 年份:ISSCC 2012