技术领域

Wireline I/O

300 篇相关论文 (2008–2026)

ISSCC 2011 Session 20 Wireline I/O
A 5.4Gb/s Adaptive Equalizer Using AsynchronousSampling Histograms
Wang-Soo Kim, Chang-Kyung Seong, Woo-Young Choi
As the data rate requirements for many wireline applications increase, channel bandwidth limitation becomes a critical problem in serial interfaces. Equalizers are often used as a solution for this problem. In addition,
Yonsei University, Seoul, Korea
ISSCC 2011 Session 20 Wireline I/O
A 6Gb/s Receiver with 32.7dB Adaptive DFE-IIR Equalization
Yi-Chieh Huang, Shen-Iuan Liu
To ensure the signal integrity over a lossy channel, an analog equalizer and/or a decision-feedback equalizer (DFE) [2-6] are widely adopted in high-speed data transmission. An adaptive analog equalizer or adaptive DFE i
National Taiwan University, Taipei, Taiwan
ISSCC 2011 Session 20 Wireline I/O
A Pattern-Guided Adaptive Equalizer in 65nm CMOS
Shayan Shahramian1, Clifford Ting1, Ali Sheikholeslami1,
receivers is becoming a necessity as the data rates increase without channel improvements. Adaptive equalizers can be implemented using data-aided or non-data-aided schemes [1], with the latter requiring less area and po
Hirotaka Tamura2, Masaya Kibune2 1 University of Toronto, Toronto, Can
ISSCC 2011 Session 20 Wireline I/O
An 8.4mW/Gb/s 4-Lane 48Gb/s Multi-StandardCompliant Transceiver in 40nm Digital CMOS Technology
Mehrdad Ramezani1, Mohamed Abdalla1, Ayal Shoval1,
Marcus Van Ierssel1, Afshin Rezayee2, Angus McLaren1, Chris Holdenried1, Jennifer Pham1, Eric So1, David Cassan1, Saman Sadr1 1 Snowbush-Gennum, Toronto, Canada, now with SecureKey, Toronto, Canada 2 The bandwidth limita
ISSCC 2011 Session 20 Wireline I/O
Analog-DFE-Based 16Gb/s SerDes in 40nm CMOS That Operates Across 34dB Loss Channels at Nyquist with a Baud Rate CDR and 1.2Vpp Voltage-Mode Driver
Andrew K. Joy1, Hugh Mair2, Hae-Chang Lee3, Arnold Feldman3,
Clemenz Portmann3, Neil Bulman1, Eugenia Cordero Crespo1, Peter Hearne1, Patty Huang3, Ben Kerr1, Pulkit Khandelwal1, Franz Kuhlmann2, Shaun Lytollis1, Joaquim Machado1, Casey Morrison2, Scott Morrison2, Shahriar Rabii3,
ISSCC 2011 Session 20 Wireline I/O
A 1.0625-to-14.025Gb/s Multimedia Transceiver with Full-rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40nm CMOS
Shaolei Quan, Freeman Zhong, Wing Liu, Pervez Aziz, Tai Jing,
Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil
ISSCC 2011 Session 20 Wireline I/O
A 4-Channel 10.3Gb/s Transceiver with Adaptive Phase Equalizer for 4-to-41dB Loss PCB Channel
Yasuo Hidaka1, Takeshi Horie2, Yoichi Koyanagi2, Takashi Miyoshi2,
Hideki Osone1, Samir Parikh1, Subodh Reddy1, Toshiyuki Shibuya1, Yasushi Umezawa2, William W. Walker1 1 Fujitsu Laboratories of America, Sunnyvale, CA, Fujitsu Laboratories, Kawasaki, Japan 2 In multi-Gb/s wireline commu
ISSCC 2010 Session 8 Wireline I/O
A 20Gb/s 40mW Equalizer in 90nm CMOS Technology
Sameh A Ibrahim, Behzad Razavi
In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transfo
University of California, Los Angeles, CA
ISSCC 2010 Session 8 Wireline I/O
A 5Gb/s Transceiver with an ADC-Based Feedforward CDR and CMA Adaptive Equalizer in 65nm CMOS
Hisakatsu Yamaguchi1, Hirotaka Tamura1, Yoshiyasu Doi1,
Yasumoto Tomita1, Takayuki Hamada1, Masaya Kibune1, Shuhei Ohmoto2, Keita Tateishi2, Oleksiy Tyshchenko3, Ali Sheikholeslami3, Tomokazu Higuchi2, Junji Ogawa1, Tamio Saito1, Hideki Ishida4, Kohtaroh Gotoh4 1 Fujitsu Labo
ISSCC 2010 Session 8 Wireline I/O
A Fractional-Sampling-Rate ADC-Based CDR with Feedforward Architecture in 65nm CMOS
Oleksiy Tyshchenko1, Ali Sheikholeslami1, Hirotaka Tamura2,
CDRs take digital samples of the received signal to recover the clock and data. Digital representation of the signal allows for extensive channel equalization in the digital domain. Recently-reported ADC-based CDRs sampl
Yasumoto Tomita2, Hisakatsu Yamaguchi2, Masaya Kibune2, Takuji Yamamot
ISSCC 2010 Session 8 Wireline I/O
A 12Gb/s 39dB Loss-Recovery Unclocked-DFE Receiver with Bi-dimensional Equalization
Massimo Pozzoni1, Simone Erba1, Davide Sanzogni1, Marcello Ganzerli2,
Reggio Emilia, Modena, Italy 3 University of Pavia, Pavia, Italy 2 Backplane communications are rapidly moving beyond 10 Gb/s both in networking and in hard-disk drive interconnection. Decision Feedback Equalization (DFE
Paolo Viola1, Daniele Baldi1, Matteo Repossi1, Giorgio Spelgatti3, Fra
ISSCC 2010 Session 8 Wireline I/O
A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS
Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno
Much effort has been made toward producing a high-speed multi-tap decision feedback equalizer (DFE), which would be a key component in removing intersymbol interference (ISI) in high-speed chip-to-chip communication. A l
NEC, Sagamihara, Japan
ISSCC 2010 Session 8 Wireline I/O
A 4.5mW/Gb/s 6.4Gb/s 22+1-Lane SourceSynchronous Link RX Core with Optional Cleanup PLL in 65nm CMOS
Robert Reutemann1, Michael Ruegg1, Fran Keyser2, John Bergkvist2,
Rüeschlikon, Switzerland 2 Source synchronous links are often used in server systems for multi-lane highspeed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent trackin
Daniel Dreps3, Thomas Toifl4, Martin Schmatz4 1 Miromico, Zürich, Swit
ISSCC 2010 Session 8 Wireline I/O
A 6.8mW 7.4Gb/s Clock-Forwarded Receiver with up to 300MHz Jitter Tracking in 65nm CMOS
Masum Hossain, Anthony Chan Carusone
High density multilink interfaces such as QPI and HyperTransport include a dedicated link to carry a synchronous clock from the transmitter to receiver and shared by 5 - 20 data transceivers. Sub-rate clocks ameliorate j
University of Toronto, Toronto, Canada
ISSCC 2010 Session 8 Wireline I/O
A 47×10Gb/s 1.4mW/(Gb/s) Parallel Interface in 45nm CMOS
Frank O’Mahony, Joseph Kennedy, James E. Jaussi,
reflects the growing need for lower-power chip-to-chip interfaces for computing systems. Boardlevel transceivers using a variety of low-power circuit techniques have demonstrated power efficiencies as low as 2.2mW/(Gb/s)
Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Ran
ISSCC 2009 Session 5 Wireline I/O
CMOS Optical 4-PAM VCSEL Driver with ModalDispersion Equalizer for 10Gb/s 500m MMF Transmission
Daisuke Watanabe, Atsushi Ono, Toshiyuki Okayasu
Data communication over 300m of distance, such as Ethernet standards, where the required data rate per channel reaches 10Gb/s or more, demand optical transmission [1]. Vertical-cavity surface-emitting laser (VCSEL) and m
Advantest, Gunma, Japan
ISSCC 2009 Session 5 Wireline I/O
Jitter-Reduction and Pulse-Width-Distortion Compensation Circuits for a 10Gb/s Burst-Mode CDR Circuit
Jun Terada1, Yusuke Ohtomo1, Kazuyoshi Nishimura1, Hiroaki Katsurai1,
burst-mode CDR circuit must be able to retime and reshape the input data. In this paper, a burst-mode CDR circuit is presented that achieves output-datajitter reduction of 3dB at jitter frequency of 1GHz, synchronization
Shunji Kimura2, Naoto Yoshimoto2 1 NTT, Atsugi, Japan, 2NTT, Chiba, Ja
ISSCC 2009 Session 5 Wireline I/O
A 4Gb/s Current-Mode Optical Transceiver in 0.18µm CMOS
Ji Sook Yun1, Mikyung Seo1, Booyoung Choi1, Jungwon Han1,
a number of high-speed digital interface standards have been introduced: LVDS, HDMI, DVI, etc [1]. DisplayPort is a digital display interface standard that is recently introduced in an attempt to meet future demands on t
Yunsung Eo2, Sung Min Park1 Ewha Womans University, Seoul, Korea Kwang
ISSCC 2009 Session 5 Wireline I/O
A 14mW 5Gb/s CMOS TIA with Gain-Reuse Regulated Cascode Compensation for Parallel Optical Interconnects
Sushmit Goswami, Jason Silver, Tino Copani, Wenjian Chen,
Hugh J. Barnaby, Bert Vermeire, Sayfe Kiaei Arizona State University, Tempe, AZ Short-distance parallel optical links are poised to replace copper interconnects in high throughput links between computing nodes. In the re
ISSCC 2009 Session 5 Wireline I/O
A 5.4mW 0.0035mm2 0.48psrms-Jitter 0.8-to-5GHz Non-PLL/DLL All-Digital Phase Generator/Rotator in 45nm SOI CMOS
Kyu-hyoun Kim1, Daniel M. Dreps2, Frank D. Ferraiolo3, Paul W. Coteus1,
Seongwon Kim1, Sergey V. Rylov1, Daniel J. Friedman1 1 IBM T.J. Watson, Yorktown Heights, NY IBM, Austin, TX 3 IBM, Poughkeepsie, NY and nine 4× legs, yielding a total of 40 realizable steps within a quadrant and 160 ste
ISSCC 2009 Session 5 Wireline I/O
mW 7GHz and 1.6mW 60GHz Frequency Dividers with Locking-Range Enhancement in 0.13µm CMOS
Sujiang Rong, Alan W.L. Ng, Howard C. Luong
Frequency dividers are key components for frequency synthesis in wireless and wireline communication systems. Among different types of frequency dividers, LC-based injection-locked frequency dividers (ILFDs) feature high
Hong Kong University of Science and Technology, Hong Kong, China
ISSCC 2009 Session 5 Wireline I/O
Bang-Bang Digital PLLs at 11 and 20GHz with sub200fs Integrated Jitter for High-Speed Serial Communication Applications
A. Rylyakov, J. Tierno, H. Ainspan, J.-O. Plouchart, J. Bulzacchelli,
Z. Toprak Deniz, D. Friedman IBM T.J. Watson Research Center, Yorktown Heights, NY Wireline communication applications typically require a low-phase-noise wide-tuning-range PLL. While these requirements can be met using
ISSCC 2009 Session 5 Wireline I/O
Subharmonically Injection-Locked PLLs for UltraLow-Noise Clock Generation
Jri Lee1, Huaide Wang1, Wen-Tsao Chen2, Yung-Pin Lee2, 1
In this paper, complete analysis and validation of subharmonic injection locking that can substantially reduce the PLL phase noise at negligible cost is presented. Two 20GHz PLLs based on this technique demonstrate 149 a
National Taiwan University, Taipei, Taiwan Industrial Technology Resea
ISSCC 2009 Session 5 Wireline I/O
A VDSL2 CPE AFE in 0.15µm CMOS with Integrated Line Driver
Giovanni Cesura1, Alessandro Bosi1, Francesco Rezzi1, Rinaldo Castello2,
VDSL2 transceivers use a wide analog bandwidth to achieve bit-rates in excess of 200Mb/s. For standard 6-band VDSL2, 30MHz bandwidth is required, comprising three up-stream and three down-stream signals. Since discrete m
Jenkin Chan3, SaiBun Wong3, Chi Fan Yung3 , Ovidiu Carnu4, Thomas Cho4
ISSCC 2009 Session 5 Wireline I/O
A 7.1mW 10GHz All-Digital Frequency Synthesizer with Dynamically Reconfigurable Digital Loop Filter in 90nm CMOS
Song-Yu Yang, Wei-Zen Chen
ADPLL frequency synthesizers have recently drawnsignificant research attention as the technology paradigm shifts into the nanometer CMOS arena [1-5]. They circumvent several design issues that conventional charge-pump-ba
National Chiao Tung University, Hsinchu, Taiwan
ISSCC 2008 Session 5 Wireline I/O
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration
Hyung-Joon Chi1, Jae-Seung Lee1, Seong-Hwan Jeon1,
2Gb/s single-ended current-integrating DFE receiver with 8b parallel data for 2-drop DRAM interface is implemented in a 0.18µm CMOS process. The reference voltage for the receiver is generated internally to reduce the ex
Seung-Jun Bae2, Jae-Yoon Sim1, Hong-June Park1 1 Pohang University of
ISSCC 2008 Session 5 Wireline I/O
5. 7 A T-Coil-Enhanced 8.5Gb/s High-Swing SourceSeries-Terminated Transmitter in 65nm Bulk CMOS
Marcel Kossel, Christian Menolfi, Jonas Weiss, Peter Buchmann,
the advantage of providing a large range of termination voltages, making them particularly suitable for multi-standard I/Os [1, 2]. Many standards (e.g. [3]) however, call for larger vertical eye openings that require ra
George von Bueren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin Sch
ISSCC 2008 Session 5 Wireline I/O
A Serial Data Transmitter for Multiple 10Gb/s Communication Standards in 0.13µm CMOS
Andrew C. Y. Lin, Marc J. Loinaz
Aeluros, Mountain View, CA The demand for higher speed and port densities in data networks has resulted in multiple 10Gb/s serial communication standards. For optical networks, this demand has spurred the development of
ISSCC 2008 Session 5 Wireline I/O
A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13µm CMOS stringent specification of >60dB linearity over the frequency band of 1 to 400MHz on the combined output of TXDAC, ECDAC and the subtraction circuit within the PGA.
Sandeep Gupta, Jose Tellado, Sridhar Begur, Frank Yang,
Vishnu Balan, Michael Inerfield, Dariush Dabiri, John Dring, Sachin Goel, Kumaraguru Muthukumaraswamy, Frank McCarthy, Glenn Golden, Jiangfeng Wu, Susan Arno, Sanjay Kasturia The architecture for both the TX and EC DAC i
ISSCC 2008 Session 5 Wireline I/O
A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude
H. Uchiki1, Y. Ota1, M. Tani2, Y. Hayakawa1, K. Asahina1, 1
are the main challenges for robust communication. Reflection in transmission line (T-line) can be reduced by proper Tline design. But ISI stems from LPF characteristics of the actual Tline and becomes severe as either th
Renesas Technology, Itami, Japan, 2Renesas Design, Itami, Japan In int
ISSCC 2008 Session 5 Wireline I/O
A 20Gb/s Duobinary Transceiver in 90nm CMOS
Jri Lee, Ming-Shuan Chen, Huai-De Wang
The ever growing volume of backplane communications pushes the data rate toward 20Gb/s for the next-generation transceivers. Over the years, chip designers have been seeking different data formats to overcome the loss of
National Taiwan University, Taipei, Taiwan
ISSCC 2008 Session 5 Wireline I/O
A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR
Chih-Fan Liao, Shen-Iuan Liu
Modern broadband communication systems require high-speed receivers to process serial data at tens of gigabits per second. As the data rate reaches 40Gb/s, skin-effect and dielectric loss in the transmission medium cause
National Taiwan University, Taipei, Taiwan
ISSCC 2008 Session 5 Wireline I/O
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane
K. Fukuda1, H. Yamashita1, F. Yuki1, M. Yagyu1, R. Nemoto1,
T. Takemoto1, T. Saito1, N. Chujo2, K. Yamamoto2, H. Kanai2, A. Hayashi1 1 Hitachi, Tokyo, Japan, 2Hitachi, Kanagawa, Japan IT systems such as servers and routers need high-speed lowerpower area-efficient chip-to-chip in
ISSCC 2008 Session 25 Wireline I/O
An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery
Ankur Agrawal1, Pavan Kumar Hanumolu2, Gu-Yeon Wei1, 1
high-performance computing systems that enable high-throughput CPUto-CPU and CPU-to-memory data transfers. Slower wide-bus interfaces have been replaced by a narrower collection of higherspeed serial links (e.g., FBDIMM
Harvard University, Cambridge, MA Oregon State University, Corvallis,
ISSCC 2008 Session 25 Wireline I/O
mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology
Kun-Hung Tsai, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu
The frequency divider (FD) [1,2] is one of the key components in very-high-frequency (VHF) PLLs. Conventionally, injection-locked frequency divider (ILFD) [3], Miller frequency divider [4], and CML static divider are wid
National Taiwan University, Taipei, Taiwan
ISSCC 2008 Session 25 Wireline I/O
A 90nm CMOS Dual-Channel Powerline Communication AFE for Homeplug AV with a Gb Extension
Keith Findlater1, Toby Bailey1, Adria Bofill2, Neil Calder1,
Seyed Danesh1,3, Robert Henderson3, William Holland1, Jed Hurwitz1, Steve Maughan3, Alasdair Sutherland1, Ewan Watt1 Gigle Semiconductor, Edinburgh, United Kingdom, Gigle Semiconductor, Barcelona, Spain, 3 University of
ISSCC 2008 Session 25 Wireline I/O
A 1.8W 115Gb/s Serial Link for Fully Buffered DIMM with 2.1ns Pass-Through Latency in 90nm CMOS
Dirk Pfaff, Sivakumar Kanesapillai, Volodymyr Yavorskyy,
Carlos Carvalho, Reza Yousefi, Muhammad Ali Khan, Trevor Monson, Mark Ayoub, Claus Reitlingshoefer Diablo Technologies, Gatineau, Canada Bandwidth and capacity of memory systems based on commodity DIMM are limited by the
ISSCC 2008 Session 25 Wireline I/O
A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS
Daeik D. Kim, Jonghae Kim, Choongyeun Cho
As an essential clock-system component, millimeter-wave dividers have been implemented for V- and W-band channels [1-8]. This has also served as a standard benchmark vehicle that reveals highspeed and low-power performan
IBM, Hopewell Junction, NY
ISSCC 2008 Session 25 Wireline I/O
A 2.6mW 370MHz–to-2.5GHz Open-Loop Quadrature Clock Generator
Kyu-hyoun Kim1, Paul W. Coteus1, Daniel Dreps2, Seongwon Kim1,
Sergey V. Rylov1, Daniel J. Friedman1 1 IBM T.J. Watson, Yorktown Heights, NY IBM, Austin, TX 2 Quadrature-phase clock generation is required for many applications in wireless and wireline communications. Traditional clo
ISSCC 2008 Session 25 Wireline I/O
A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion
Tomoaki Kawamura1, Yusuke Ohtomo1, Kazuyoshi Nishimura1, Noboru Ishihara2
NTT, Atsugi, Japan Gunma University, Kiryu, Japan 2 The data-timing generator (DTG) presented herein provides a delay of over 20× of the 10Gb/s data cycle, and operates over the wide frequency range of DC to 11Gb/s. The
ISSCC 2008 Session 25 Wireline I/O
An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL Sander Gierkink
Conexant Systems, Red Bank, NJ, DLL clock multipliers outperform their PLL counterparts in terms
of phase noise because they have significantly less jitter accumulation [1,2,3]. Figure 25.2.1 shows the basic PLL and recirculating DLL. In the latter, the oscillator loop is periodically opened to let in a “clean” refe
ISSCC 2008 Session 25 Wireline I/O
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS
Frank O’Mahony1, Sudip Shekhar2, Mozhgan Mansuri1, Ganesh Balamurugan1,
James E. Jaussi1, Joseph Kennedy1, Bryan Casper1, David J. Allstot2, Randy Mooney1 Intel, Hillsboro, OR, 2University of Washington, Seattle, WA 1 With the rise in aggregate bandwidth of microprocessors, there is an ever-
ISSCC 2008 Session 11 Wireline I/O
A 10Gb/s MLSE-based Electronicd-DispersionCompensation IC with Fast Power-Transient Management for WDM Add/Drop Networks
Hyeon-Min Bae1, Jonathan Ashbrook1, Naresh Shanbhag2, Andrew Singer2
Finisar Corporation, Champaign, IL University of Illinois at Urbana-Champaign, Urbana, IL 2 Optical add/drop multiplexers (OADM) are being used in WDM networks to improve bandwidth efficiency by reconfiguring channel cap
ISSCC 2008 Session 11 Wireline I/O
A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s
Oscar Agazzi1,2, Diego Crivelli2, Mario Hueda2, Hugo Carrer2, Germán Luna2,
Ali Nazemi1, Carl Grace1, Bilal Kobeissy1, Cindra Abidin1, Mohammad Kazemi1, Mahyar Kargar1, César Marquez1, Sumant Ramprasad1, Federico Bollo2, Vladimir Posse1, Stephen Wang1, Georgios Asmanis1, George Eaton1, Norman Sw
ISSCC 2008 Session 11 Wireline I/O
A 96Gb/s-Throughput Transceiver for ShortDistance Parallel Optical Links
Sushmit Goswami1, Tino Copani1, Anuj Jain1, Habib Karaki1,
Bert Vermeire1, Hugh J. Barnaby1, Greg Fetzer2, Rick Vercillo2, Sayfe Kiaei1 Arizona State University, Tempe, AZ, 2Arete Associates, Tucson, AZ local decoupling capacitors are placed within every channel. If adjacent cha
ISSCC 2008 Session 11 Wireline I/O
A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback
Hidemi Noguchi1, Nobuhide Yoshida1, Hiroaki Uchida2,
the CDR circuit is not often the optimum position of the eye diagram. For example, asymmetrical waveform distortion, internal delay mismatch, or internal voltage offset causes the misalignment of the decision point in th
Manabu Ozaki2, Shunichi Kanemitsu2, Shigeki Wada1 1 NEC, Kanagawa, Jap
ISSCC 2008 Session 11 Wireline I/O
A 10.3125Gb/s Burst-Mode CDR Circuit using a ΔΣ DAC
Jun Terada1, Kazuyoshi Nishimura1, Shunji Kimura2,
transmission that has an instantaneous response, tolerance to long consecutive-identical digits (CIDs), and high jitter tolerance. In this paper, a burst-mode CDR circuit achieves instantaneous locking of 1b, CID toleran
Hiroaki Katsurai1, Naoto Yoshimoto2, Yusuke Ohtomo1 1 NTT, Atsugi, Jap
ISSCC 2008 Session 11 Wireline I/O
A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells
Che-Fu Liang, Shen-Iuan Liu
PON is one of the promising solutions for the last-mile communication systems. In PONs, the fast-locked CDR circuit must lock within tens of bit times once the data packets arrive. The socalled burst-mode CDR (BMCDR) cir
National Taiwan University, Taipei, Taiwan
ISSCC 2008 Session 11 Wireline I/O
A 10Gb/s Laser-Diode Driver with Active BackTermination in 0.18µm CMOS
Chia-Ming Tsai, Mao-Cheng Chiu
A laser-diode driver (LDD) requires output transmission-line back-termination that absorbs signal reflection from the imperfectly terminated load, especially when a low-cost laser diode is used to build a high-speed opti
National Chiao Tung University, Hsinchu, Taiwan
ISSCC 2008 Session 11 Wireline I/O
A 2.7V 9.8Gb/s Burst-Mode TIA with Fast Automatic Gain Locking and Coarse Threshold Extraction
Tine De Ridder1, Peter Ossieur2, Bart Baekelandt3, Cedric Mélange3,
Integrated Photonics, Ipswich, United Kingdom 3 Today’s broadband access is moving towards PONs at 10Gb/s. This requires a burst-mode receiver to support the TDMA protocol used in its upstream path [1, 2]. Such a receive
Johan Bauwelinck1, Colin Ford4, Xing-Zhi Qiu1, Jan Vandewege1 1 Ghent