⚡ 本页包含 AI 生成的分析内容,仅供参考
该论文介绍了一款采用90nm CMOS工艺的双通道电力线通信模拟前端(AFE),用于支持千兆扩展的Homeplug AV标准。它集成了增益可编程放大器(PGA)和10位流水线ADC,解决了电力线通信中的宽带信号接收问题。
Seyed Danesh1,3, Robert Henderson3, William Holland1, Jed Hurwitz1, Steve Maughan3, Alasdair Sutherland1, Ewan Watt1 Gigle Semiconductor, Edinburgh, United Kingdom, Gigle Semiconductor, Barcelona, Spain, 3 University of Edinburgh, Edinburgh, United Kingdom providing a gain range of -18 to 51dB in 3dB steps. At maximum gain, the measured in-band input-referred noise is 30µVrms. The PGA output is then digitized by a 10b pipelined ADC [3], running at 100MHz on a regulated 1.2V supply. Figure 25.7.2 shows the data rates achieved during reception of a training sequence versus gain settings. As expected, the throughput decreases at high gains, but a theoretical maximum data rate of 180Mb/s with a BER=1e-3 (without FEC) is achieved. 1 2 Powerline communications is currently emerging as a strong candidate for in-home multi-media content distribution. Recently, products have become available that support 200Mb/s rates over
Keith Findlater1, Toby Bailey1, Adria Bofill2, Neil Calder1,