ISSCC 2008
Session 1
Plenary
The 2nd Wave of the Digital Consumer Revolution: Challenges and Opportunities! Hyung Kyu Lim
From its commercial introduction in the 1950s, the digital computer consistently extended its performance through the application of semiconductor technology, and thus sparked a dramatic increase in industrial productivi
ISSCC 2008
Session 1
Plenary
Not to put too fine a spin on things, but did it ever occur to you when your meal was getting cold while you were waiting for the server to notice that your wine glass needed filling, that this was a problem that you could address through circuit design, and practically and realistically do so within the next year or so? I thought not! So what else are we missing?
library or elsewhere appear scattered on the surface. Any of these can be played by touching them. But they can also be loaded in either Zune on the Surface, just by dragging, as can the albums under the user’s hand be d
ISSCC 2008
Session 1
Plenary
Embedded Processing at the Heart of Life and Style Mike Muller
From pacemakers through mobile phones to passenger jets, most people deal with electronic devices empowered by embedded processor cores, every day, without a second thought. This penetration into everyday lives across su
ISSCC 2008
Session 1
Plenary
Why Can’t A Computer Be More Like A Brain? Or What To Do With All Those Transistors? Jeff Hawkins
Why is it so difficult for computers to perform tasks that humans do quickly and easily? For over fifty years, we have tried to program computers to recognize images, understand language, control robots, and learn on the
ISSCC 2008
Session 10
RF & Wireless
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE
therefore the amount of power/substrate-noise coupling to DCO core is greatly reduced, improving spur performance. To further suppress switching noise, the simple RC filter can be turned on to linearize a hard-switching
ISSCC 2008
Session 10
RF & Wireless
Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control
Christopher Jones1, Paul Fowers1, Steve Brett1, Christophe Beghein1, Federico Beffa2 1 MediaTek, West Malling, United Kingdom Federico Beffa Engineering, Agno, Switzerland 2 With growing WCDMA adoption there is a strong
ISSCC 2008
Session 10
RF & Wireless
Equalization of IM3 Products in Wideband DirectConversion Receivers
As scaling reduces the breakdown voltage of CMOS devices and as system integration trends demand the further elimination of offchip components, there arises a great need to improve the linearity of RF receivers. Of parti
ISSCC 2008
Session 10
RF & Wireless
A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13µm CMOS
T. Li, Z. Zhou, P. Lettieri, Y. Chang, A. Hadji, P. Chang, M. Nariman, I. Bhatti, A. Medi, L. Serrano, J. Welz, K. Shoarinejad, S. Hasan, J. Castaneda, J. Kim, H. Tran, P. Kilcoyne, R. Chen, B. Lee, B. Zhao, B. Ibrahim,
ISSCC 2008
Session 10
RF & Wireless
A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS
I. Bashir, C.-M. Hung, J. Wallberg, R. Staszewski, P. Cruise, S. Rezeq, S. Vemulapalli, K. Waheed, N. Barton, M.-C. Lee, C. Fernando, K. Maggio, T. Jung, I. Elahi, S. Larson, T. Murphy, G. Feygin, I. Deng, T. Mayhugh, Y.
ISSCC 2008
Session 10
RF & Wireless
Integration of a SiP for GSM/EDGE in CMOS Technology pulse-width-modulation (PWM) controlled vibrator drive and a 400mW audio amplifier for driving 8Ω loudspeakers.
Braam Greyling4, Salvatore Piccolella5 The RF transceiver (Fig. 10.6.2) is connected via an on-chip serial interface to the BB part avoiding the need of any off-chip interconnection between BB and RF. This on-chip connec
ISSCC 2008
Session 10
RF & Wireless
A Low-Power WCDMA Transmitter with an Integrated Notch Filter
In a WCDMA FDD system, since the transmitter and receiver operate concurrently, the receiver is plagued by the transmitter leakage due to finite isolation of antenna duplexer. As a consequence, the transmitter noise at t
ISSCC 2008
Session 10
RF & Wireless
A 1.2V 0.2-to-6.3GHz Transceiver with Less Than −29.5dB EVM@−3dBm and a Choke/Coil-Less PrePower Amplifier
2V 0.2-to-6.3GHz transceiver for a multimode radio is fabricated in a 0.13µm CMOS technology. Figure 10.8.1 shows the measured matching characteristics of the transmitter (S22), receiver (S11) and EVM of the transmitted
ISSCC 2008
Session 10
RF & Wireless
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS
in the design of Ka band and mm-wave silicon ICs has motivated several industrial projects toward the realization of chipsets for broadband communications and automotive cruise control applications. Performance of standa
ISSCC 2008
Session 11
Wireline I/O
A 2.7V 9.8Gb/s Burst-Mode TIA with Fast Automatic Gain Locking and Coarse Threshold Extraction
Integrated Photonics, Ipswich, United Kingdom 3 Today’s broadband access is moving towards PONs at 10Gb/s. This requires a burst-mode receiver to support the TDMA protocol used in its upstream path [1, 2]. Such a receive
ISSCC 2008
Session 11
Wireline I/O
A 10Gb/s Laser-Diode Driver with Active BackTermination in 0.18µm CMOS
A laser-diode driver (LDD) requires output transmission-line back-termination that absorbs signal reflection from the imperfectly terminated load, especially when a low-cost laser diode is used to build a high-speed opti
ISSCC 2008
Session 11
Wireline I/O
A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells
PON is one of the promising solutions for the last-mile communication systems. In PONs, the fast-locked CDR circuit must lock within tens of bit times once the data packets arrive. The socalled burst-mode CDR (BMCDR) cir
ISSCC 2008
Session 11
Wireline I/O
A 10.3125Gb/s Burst-Mode CDR Circuit using a ΔΣ DAC
transmission that has an instantaneous response, tolerance to long consecutive-identical digits (CIDs), and high jitter tolerance. In this paper, a burst-mode CDR circuit achieves instantaneous locking of 1b, CID toleran
ISSCC 2008
Session 11
Wireline I/O
A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback
the CDR circuit is not often the optimum position of the eye diagram. For example, asymmetrical waveform distortion, internal delay mismatch, or internal voltage offset causes the misalignment of the decision point in th
ISSCC 2008
Session 11
Wireline I/O
A 96Gb/s-Throughput Transceiver for ShortDistance Parallel Optical Links
Bert Vermeire1, Hugh J. Barnaby1, Greg Fetzer2, Rick Vercillo2, Sayfe Kiaei1 Arizona State University, Tempe, AZ, 2Arete Associates, Tucson, AZ local decoupling capacitors are placed within every channel. If adjacent cha
ISSCC 2008
Session 11
Wireline I/O
A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s
Ali Nazemi1, Carl Grace1, Bilal Kobeissy1, Cindra Abidin1, Mohammad Kazemi1, Mahyar Kargar1, César Marquez1, Sumant Ramprasad1, Federico Bollo2, Vladimir Posse1, Stephen Wang1, Georgios Asmanis1, George Eaton1, Norman Sw
ISSCC 2008
Session 11
Wireline I/O
A 10Gb/s MLSE-based Electronicd-DispersionCompensation IC with Fast Power-Transient Management for WDM Add/Drop Networks
Finisar Corporation, Champaign, IL University of Illinois at Urbana-Champaign, Urbana, IL 2 Optical add/drop multiplexers (OADM) are being used in WDM networks to improve bandwidth efficiency by reconfiguring channel cap
ISSCC 2008
Session 12
Data Converters
An 820µW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/mediumbandwidth range [
ISSCC 2008
Session 12
Data Converters
Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS
to the highest combination of resolution and speed in pipelined ADCs [1,2] and has made the sampling rate of SAR ADCs competitive with flash ADCs [3,4], but several challenges exist. As every sample must be accurate, per
ISSCC 2008
Session 12
Data Converters
A 150MS/s 133µW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous BinarySearch sub-ADC
in medium- to high-speed (10s of MS/s to a few GS/s) and medium- to low-resolution (4b to 9b) A/D converters. Current state-of-the-art FOM is 65fJ [1]. These efficiency improvements are primarily driven by mobile, wirele
ISSCC 2008
Session 12
Data Converters
A 1.9µW 4.4fJ/Conversion-step Charge-Redistribution ADC 10b 1MS/s
Future systems powered by energy scavenging, e.g., wireless sensor nodes, demand μW-range ADCs with no static bias currents in order to have a power dissipation proportional to the sample rate. An ADC that meets these re
ISSCC 2008
Session 12
Data Converters
A 9.4-ENOB 1V 3.8µW 100kS/s SAR ADC with TimeDomain Comparator
The signal bandwidth used in portable or autonomous sensor systems is often lower than 50kHz with ADC requiring about 8 to 10 bits resolution, but the consumed power must be very low: few μW or a FOM = P/(2ENoBfsampl) lo
ISSCC 2008
Session 12
Data Converters
A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC
University of Texas, Austin, TX, 2National Semiconductor, Salem, NH Low-power consumption is a key specification in many electronic systems, such as wireless communication and imaging systems. One of the most efficient w
ISSCC 2008
Session 12
Data Converters
A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS
Applications using broadband digital wireless modulation require high-resolution low-power ADC over a bandwidth of few megahertz. For a WiFi or a WiMAX standard, an ADC of ~10b resolution in 5 to 20MHz bandwidth is neede
ISSCC 2008
Session 12
Data Converters
A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS
IMEC, Leuven, Belgium Vrije Universiteit Brussel, Brussel, Belgium 2 High-speed low-resolution ADCs are an essential part of receivers for wireless standards such as UWB. These converters have to combine the stringent sp
ISSCC 2008
Session 13
Digital Processors
A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-κ Metal Gate CMOS
specifically designed for Mobile Internet Devices (MID) and UltraMobile PCs (UMPC) where average power consumed is in the order of a few hundred mW (as measured by MobileMark’05 OP @ 60 nits brightness) with performance
ISSCC 2008
Session 13
Digital Processors
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques benefits of FBB and RBB (Fig. 13.2.3). This ABB approach achieves an optimal balance of performance and power with circuit techniques alone, eliminating the need for additional LVT or HVT logic transistors.
Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko The device has 16Mb of SRAM and
ISSCC 2008
Session 13
Digital Processors
A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU 1 1 1 1
Kenichi Nitta1, Takao Koike1, Shinichi Yoshioka1, Koji Ohno1, Masahito Saigusa2, Minoru Sakata3, Yukio Kodama4, Yuji Arai5, Teruyoshi Komuro6 1 Renesas Technology, Tokyo, Japan, 2NTT DoCoMo, Tokyo, Japan Fujitsu, Kanagaw
ISSCC 2008
Session 13
Digital Processors
A 9.7mW AAC-Decoding, 620mW H.264 720p
Shuou Nomura1, Fumihiko Tachibana1, Tetsuya Fujita1, Chen Kong Teh1, Hiroyuki Usui1, Fumiyuki Yamane1, Yukimasa Miyamoto1, Chaiyasit Kumtornkittikul1, Hiroyuki Hara1, Takahiro Yamashita1, Jun Tanabe1, Masato Uchiyama1, Y
ISSCC 2008
Session 13
Digital Processors
A 58mW 1.2mm² HSDPA Turbo Decoder ASIC in 0.13µm CMOS
provide a compelling user experience has made HSPA an indispensable catalyst for a substantial subscriber transition from 2G to 3G [1]. Data rates reaching the full potential of 3GPP R6 from cost-effective mobile termina
ISSCC 2008
Session 13
Digital Processors
An 11mm2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12µm CMOS
Rapid evolution of wireless standards and the increasing demand for multi-standard products make traditional fixed-function hardware for baseband processing too rigid. Programmable solutions are needed. At the same time,
ISSCC 2008
Session 14
Memory
A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS
Cormac O’Connelll, Sreedhar Natarajan1, Chris Huang2, Chuan-Yu Wu2, Min-Jer Wang2, C. J. Wang2, Paul Chen2, Rick Hsieh2 1 TSMC Design Technology Canada, Kanata, Canada TSMC, Hsinchu, Taiwan 2 From 90nm and below, SoC int
ISSCC 2008
Session 14
Memory
A 170GB/s 16Mb Embedded DRAM with Data-Bus Charge-Recycling
Mike Mound1, G.W. Jones1, Tim Egging1, Tomofumi Arakawa2, Katsuhiko Sasahara2, Kazuo Taniguchi2, Masayuki Miyabayashi2 United Memories, Colorado Springs, CO Sony Corporation, Tokyo, Japan driven to VCC and one of the GDR
ISSCC 2008
Session 14
Memory
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process
Muhammad Khellah, Jason Howard, Greg Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi Intel, Hilsboro, OR As silicon technology scales, the possibility of fabricating dense memories [1-4] is of great inter
ISSCC 2008
Session 14
Memory
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications
Atsushi Suzuki1, Tomohisa Takai1, Naoko Itoga1, Takayuki Miyazaki1, Takayuki Iwai1, Hiroyuki Takenaka2, Takehiko Hojo1, Shinji Miyano1, Nobuaki Otsuka1 1 Toshiba, Kawasaki, Japan, 2Toshiba Microelectronics, Kawasaki, Jap
ISSCC 2008
Session 14
Memory
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
Dae-Hyun Chung, Jin-Gook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim, Hye-Ran Kim, Yong-Jae Shin, Cheol-Goo Park, Gil-Shin Moon, Ki-Woong Yeom, Ka
ISSCC 2008
Session 14
Memory
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface
Young Kyoung Choi, Jung Woo Lee, Seung Wook Kwack, Hyeong Ouk Lee, Won Joo Yun, Sang Hoon Shin, Kwan Weon Kim, Young Jung Choi, Ye Seok Yang Hynix Semiconductor, Icheon, Korea After the development of graphics DRAM inter
ISSCC 2008
Session 14
Memory
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology
Ji Yeon Yang, Hyeng Ouk Lee, Dong Uk Lee, Sujeong Sim, Young Ju Kim, Won Jun Choi, Keun Soo Song, Sang Hoon Shin, Hyang Hwa Choi, Hyung Wook Moon, Seung Wook Kwack, Jung Woo Lee, Young Kyoung Choi, Nak Kyu Park, Kwan Weo
ISSCC 2008
Session 15
Power Management
A CMOS-SOI 2.45GHz Remote-Powered Sensor Tag
To enable the wide deployment of ambient intelligence, where various environmental parameters can be sensed and reported, the main challenge consists in developing low-cost, low-power and miniaturized sensor tags compose
ISSCC 2008
Session 15
Power Management
A Triple-Band Passive RFID Tag
Graz University of Technology, Graz, Austria, 2Infineon, Graz, Austria To profit from the application-benefits of both 13.56MHz HF RFID systems typically used in identification and 860 to 960MHz UHF RFID systems used in
ISSCC 2008
Session 15
Power Management
An Inductively-Coupled 64b Organic RFID Tag Operating at 13.56MHz with a Data Rate of 787b/s
M. J. Beenhakkers3, C. W. Sele3, N. A. J. M. van Aerle3, G. H. Gelinck4, J. Genoe1, P. Heremans1,2 1 IMEC, Leuven, Belgium, 2K. U. Leuven, Leuven, Belgium Polymer Vision, Eindhoven, The Netherlands 4 TNO Science and Indu
ISSCC 2008
Session 15
Power Management
A 107pJ/b 100kb/s 0.18µm Capacitive-Coupling Transceiver for Printable Communication Sheet
Yoshiaki Noguchi1, Shintaro Nakano1, Koichiro Zaitsu1, Tadahiro Kuroda2, Takao Someya1, Takayasu Sakurai1 1 University of Tokyo, Tokyo, Japan, 2Keio University, Yokohama, Japan Low-power wireless communications between e
ISSCC 2008
Session 15
Power Management
Next Generation Smart Power Technologies – Challenges and Innovations Enabling Complex SoC Integration
on-chip computing power, higher speed and more memory, a second “More-than-Moore” trend is becoming increasingly important. These strongly application-driven technologies focus on the interface between the “analog world”
ISSCC 2008
Session 15
Power Management
An 11Gb/s Inductive-Coupling Link with Burst Transmission 1 1 1
solutions for highspeed short-range wireless communications between stacked chips. Figure 15.7.1 plots data rate and communication distance of the capacitive and the inductive-coupling links [1-12]. A capacitivecoupling
ISSCC 2008
Session 15
Power Management
Capacitive Power-Management Circuit for Micropower Thermoelectric Generators with a 2.1µW Controller
U.Leuven, Heverlee, Belgium R. M. A., Brussels, Belgium 3 Energy scavenging [1] is an emerging method to power energyautonomous wireless sensor systems by converting ambient environmental energy into electrical energy. M
ISSCC 2008
Session 15
Power Management
A Full-Wave Rectifier for Interfacing with MultiPhase Piezoelectric Energy Harvesters
Many mechanical vibration-based energy harvesting systems use a piezoelectric transducer as an AC power source, whose output voltage must first be rectified before being delivered to a load. For ultra-low power (<1mW) sy
第 1/5 页 · 共 228 篇 · 下一页 →