Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS

📋 论文概要

本文提出了一种高度交错的5位250MS/s ADC，采用36个时间交错SAR ADC通道和冗余通道策略，在65nm CMOS工艺下以800mV低电压运行，通过并行化提高能效并解决通道间时序偏差和良率问题。

💡 主要创新点

• 利用时间交错和冗余通道技术，在5位分辨率下实现250MS/s采样率，通过通道间冗余提高良率并降低时序偏差影响。
• 在65nm CMOS工艺下采用800mV低电压供电，通过高度并行化提升能量效率，同时优化时钟分布开销。

🏷 关键词

📄 原文摘要

to the highest combination of resolution and speed in pipelined ADCs [1,2] and has made the sampling rate of SAR ADCs competitive with flash ADCs [3,4], but several challenges exist. As every sample must be accurate, performance is limited by the worst channel; thus, local variation degrades yield. Timing skew between channels introduces distortion and is difficult to correct digitally. Finally, clock distribution is a significant overhead. The 250MS/s ADC has 36 time-interleaved 5b SAR ADC channels operating at 800mV. Parallelism is used specifically to improve energy efficiency, and architectural solutions address the limitations of interleaving. Redundancy is used as an efficient technique to counteract the yield loss from local variation. A hierarchical topplate sampling network reduces timing skew with extended sampling times and permi

👥 作者与机构

Brian P. Ginsburg1, Anantha P. Chandrakasan2, 1

Texas Instruments, Dallas, TX Massachusetts Institute of Technology, Cambridge, MA 2 Time-interleaving is a well established technique that has led