A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction

📋 论文概要

该论文提出了一种3GHz分数N全数字锁相环（ADPLL），通过精确的时间数字转换器（TDC）校准和失配校正技术，解决了传统TDC线性度不足导致杂散含量高的问题，实现了宽带操作和低杂散性能。

💡 主要创新点

• 提出了一种精确的TDC校准方法，提高了TDC的线性度，降低了量化噪声。
• 引入了失配校正技术，补偿了TDC单元间的失配，进一步改善了PLL的杂散性能。
• 实现了全数字架构的3GHz分数N频率合成，避免了模拟电路在先进CMOS工艺中的低电压和性能退化问题。

🏷 关键词

📄 原文摘要

area of intense investigation, motivated by low supply headroom and poor analog performance in ultra-scaled CMOS. RF frequency synthesis is particularly amenable to a digital architecture and has already seen integration benefits [1]. Nevertheless obstacles exist in the time-to-digital converter (TDC) used in an all-digital PLL (ADPLL), the equivalent of the PD and CP combination in a conventional analog PLL. To meet the requirements for wired and wireless synthesis, a synthesizer must be capable of wide-band operation as well as low spurious content, necessitating a linear TDC with fine quantization steps, such as a vernier delayline (VDL) architecture [2]; unfortunately, the architectural complexity increases sensitivity to both supply noise and device mismatch. This work introduces two techniques to amelior

👥 作者与机构

Colin Weltin-Wu1,2, Enrico Temporiti3, Daniele Baldi3, Francesco Svelto2, 1

Columbia University, 2Università degli Studi di Pavia, Pavia, Italy STMicroelectronics, Pavia, Italy 3 Developing digital implementations of analog and RF functions has become an