A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13µm CMOS

📋 论文概要

该论文提出了一种采用2位/步逐次逼近寄存器（SAR）架构的6位1.25GS/s模数转换器（ADC），在0.13µm CMOS工艺中实现了32mW的低功耗。通过利用高速数字逻辑和高度匹配的小电容器，解决了传统闪存型ADC在高速应用中功耗过高的问题。

💡 主要创新点

• 采用2位/步的SAR架构，提高了转换速率并降低了功率消耗。
• 利用高速数字逻辑和高度匹配的小电容器设计，实现了低功耗高性能的ADC。

🏷 关键词

📄 原文摘要

widely used in serial links, magnetic recording systems and UWB receivers. Flash ADCs have been dominantly used for these applications. This paper presents an ADC that takes advantage of the high-speed digital logic and highly matched small capacitors

👥 作者与机构

Zhiheng Cao1, Shouli Yan1, Yunchu Li2, 1

University of Texas at Austin, Austin, TX Analog Devices, Wilmington, MA 2 ADCs with 6b resolution and gigahertz sampling frequency are