A 45nm 4Gb 3-Dimensional Double-Stacked MultiLevel NAND Flash Memory with Shared Bitline Structure

📋 论文概要

本文提出了一种采用45nm工艺的4Gb三维双堆叠多级NAND闪存，通过共享位线结构和单晶硅层堆叠(S3)方法，实现了高密度、低成本和高性能的存储解决方案。解决了传统平面NAND闪存密度提升受限的问题。

💡 主要创新点

• 采用三维双堆叠结构，将两个NAND闪存层垂直堆叠，有效提高存储密度。
• 引入共享位线结构，减少互连复杂度，降低芯片面积和成本。
• 使用单晶硅层堆叠(S3)方法，实现高性能单晶硅通道，改善器件特性。

🏷 关键词

📄 原文摘要

Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jaehoon Jang, Han-Soo Kim, Soon-Moon Jung, Yeong-Taek Lee, Changhyun Kim and Won-Seong Lee Samsung, Hwasung, Korea Recently, 3-dimensional (3-D) memories have regained attention as a potential future memory solution featuring low cost, high density and high performance [1-6]. Among various approaches such as poly-Si and package-based wafer or chip stacking, the recently developed single-crystal Si layer stacking (S3) method is very attractive in terms of device performance and fabrication costs [4,5]. A 3D double-stacked NAND flash memory cell implemented by S3 has been previously demonstrated using 63nm CMOS technology [5]. We present a 3-D double stacked 4Gb MLC NAND flash memory device with shared BL structure, with a cell size of 0.0021µm2/bit per unit feature area. The device is designed to support 3-D stacking and fabricated by S3 and 45nm floating-gate CMOS technologies. By using Si-layer-dedicated decoder and layer-compensated

👥 作者与机构

Ki-Tae Park, Doogon Kim, Soonwook Hwang, Myounggon Kang,