An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL Sander Gierkink

📋 论文概要

该论文提出了一种结合PLL和循环DLL的时钟乘法器，通过周期性打开振荡器以引入干净参考边沿，解决了传统边缘组合DLL中延迟级失配导致的图案抖动以及鉴相器/电荷泵静态相位偏移引起的相位不连续性问题。实现了800MHz输出频率和-122dBc/Hz@200kHz的相位噪声性能。

💡 主要创新点

• 将PLL与循环DLL相结合，利用循环DLL周期性地重置振荡器环路，注入干净参考边沿，有效抑制了抖动累积。
• 通过消除延迟级失配引起的图案抖动，并降低静态相位偏移导致的相位不连续性，改善了时钟频谱纯度。

🏷 关键词

📄 原文摘要

of phase noise because they have significantly less jitter accumulation [1,2,3]. Figure 25.2.1 shows the basic PLL and recirculating DLL. In the latter, the oscillator loop is periodically opened to let in a “clean” reference edge. It avoids the pattern jitter due to delaystage mismatch as seen normally in an edge-combining DLL. The remaining pattern jitter is due to static phase offset of the phase detector (PD)/charge pump (CP). This offset transfers to a phase discontinuity between the two edges that are substituted for one another [2]. As a result the clock spectrum shows severe reference spurs, as high as -37dBc in [1]. This is especially undesirable in applications like ADCs where clock spurs convolute with the spectrum of the input signal. By contrast, in a PLL, static phase offset introduces no direct phase discontinuity in the output clock. Nevertheless, it still causes a periodic ripple across the loop filter

👥 作者与机构

Conexant Systems, Red Bank, NJ, DLL clock multipliers outperform their PLL counterparts in terms