A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor

📋 论文概要

该论文介绍了一款采用65nm工艺、集成2.05亿晶体管的四核安腾处理器，包含30MB缓存，核心频率达2.0GHz。通过电路方法学增强和缓存优化，实现了低电压操作和低待机功耗，解决了高集成度与低功耗的矛盾。

💡 主要创新点

• 集成四个双线程核心和30MB片上缓存，相比前代产品核心数翻倍。
• 采用电路方法学增强技术，支持低电压（VCCMIN）操作，提升能效。
• 优化缓存设计，降低待机功耗并改善VCCMIN特性。

🏷 关键词

📄 原文摘要

The processor has 4 dual-threaded cores integrated on die with a system interface and 30MB of cache in an 8M 65nm process. The 21.5×32.5mm2 die contains 2.05 billion transistors (Fig. 4.6.1). The silicon is designed to operate the cores up to 2.0GHz and the system interface at 2.4GHz, with a thermal design power (TDP) of 170W at 110°C. Improvements over previous designs include the integration of two additional cores on the die [1,2] with circuit methodology enhancements for low-voltage operation. The caches are optimized for improved VCCMIN and low standby power operation. New to the chip is the inclusion of high-speed interconnects, the integration of a system interface using SER-tolerant storage elements, the implementation of a fully deterministic power-frequency management system, and the design of a tunable di/dt

👥 作者与机构

Blaine Stackhouse1, Brian Cherkauer1, Mike Gowan,

Paul Gronowski2, Chris Lyles1 1 Intel, Fort Collins, CO, 2Intel, Hudson, MA The next generation in the Itanium processor family is introduced