A 400µW 4.7-to-6.4GHz VCO under an Above-IC Inductor in 45nm CMOS

📋 论文概要

该论文提出了一种在45nm CMOS工艺中利用Above-IC技术（后处理高Q电感）实现的低功耗VCO，通过将VCO完全布局在电感下方并采用两层屏蔽实现3D集成，在400µW功耗下实现了4.7-6.4GHz的频率调谐范围。

💡 主要创新点

• 采用Above-IC技术（5μm电镀铜层+18μm低K BCB介质）实现高Q电感，降低VCO功耗。
• 将VCO有源电路完全布局在电感下方，利用CMOS后道顶层两层屏蔽实现3D集成，节省芯片面积。

🏷 关键词

📄 原文摘要

performance attainable in already available technologies. Above-IC technology (A-IC), consisting of a 5μm thick electroplated Cu layer on an 18μm low-K BCB dielectric, post-processed on top of the CMOS, provides a low-cost solution to achieve high-Q passive devices [1], with relaxed mask requirements. For example, inductors with very high quality factors can be designed that are beneficial for low-power circuits. A technique is presented to fully layout a VCO under its A-IC inductor, by using a two-layer shield in the top layers of the CMOS back-end, enabling 3D integration of active circuitry and high-Q passives. The technique is demonstrated on an LC-VCO in 45nm bulk CMOS, that consumes only 400μW, and occupies a low area of 0.12mm2. To regain silicon area under inductors, placing devices underneath

👥 作者与机构

J. Borremans1,2, P. Wambacq1,2, M. Kuijk2, G. Carchon1, S. Decoutere1, 1

IMEC, Leuven, Belgium, 2Vrije Universiteit Brussel, Brussels, Belgium With the increasing cost of scaled CMOS, effort is spent in maximizing