A 32kb 10T Subthreshold SRAM Array with BitInterleaving and Differential Read Scheme in 90nm CMOS

📋 论文概要

该论文提出了一种采用10T存储单元和差分读取方案的低压亚阈值SRAM，实现了位交错结构以增强软错误免疫性，解决了传统单端读取方案中位线摆幅受限和无法有效位交错的问题。

💡 主要创新点

• 提出10T存储单元结合差分读取方案，在亚阈值电压下实现稳定的读写操作，克服了单端读取的噪声和摆幅限制。
• 首次在亚阈值SRAM中实现高效的位交错列结构，显著提升了多比特软错误的免疫能力。

🏷 关键词

📄 原文摘要

J. Watson, Yorktown Heights, NY 2 For robust subthreshold SRAMs, 8T or 10T subthreshold SRAMs based on single-ended read sensing have been proposed [1-3]. While the schemes in [1-3] improve the read stability and writability significantly, their single-ended sensing methods still suffer from reduced bitline swing due to bitline noise. In addition, the previous schemes do not have efficient bit-interleaving in the column structure, which is critical to cope with multiple-bit soft errors [4]. In this paper, we present a 10T subthreshold SRAM with efficient bit-interleaving for soft-error immunity and fully differential read for better stability. Figure 21.7.1 shows the 10T SRAM cell. In read mode, WL is enabled and VGND is forced to ground while W_WL remains disabled as shown in the timing diagram. Since the disabled W_WL makes the nodes ‘Q’ and ‘QB’ isolated from the bitlines during the

👥 作者与机构

Ik Joon Chang1, Jae-Joon Kim2, Sang Phill Park1, Kaushik Roy1, 1

Purdue University, West Lafayette, IN, IBM T